Toshiba SD-1300A, Service Manual

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3-23
Table 3-5-3 TMP87CH74AF-2C07 (2/2)
Pin
No.
73
|
77
9,8
10
13
40,7
78
39,
38
Function
5 bit high dielectric strength I/O port.
When using as the fluorescent display
driver, the output latch is cleared to “0”.
High frequency oscillator connection
terminal.
Entered XIN when the external clock input
is selected, and XOUT is opened.
Reset signal input, watch dog timer output /
address trap reset output / system clock
reset output
Terminal for shipping test. Fixed to the low
level.
+5V, 0V (GND)
Power supply terminal for fluorescent
display driving
Analog reference voltage for A/D
conversion, reference GND. VASS should
be always fixed to 0V (GND) when A/D.
Name
PD0 (V32)
|
PD4 (V36)
XIN, XOUT
RESET
TEST
VDD, VSS
VKK
VAREF,
VASS
Table 3-5-4 TMP94C251AF(Z) (1/5)
Pin
No.
70
|
77
79
|
86
108
|
115
99
|
106
90
|
97
68
67
66
65
64
63
62
60
Function
Port 0: I/O port
Data 0~7: data bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
Becomes high impedance when not
accessing to the external memory.
Port 1: I/O port
Data 8~15: data bus 8~15
Initialized to this function when starting with
data bus width higher than 16 bit in the
external ROM type, TMP94C251A.
Becomes to high impedance when not
accessing to the external memory.
Port 4: I/O port
Address 0~7: address bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 5: I/O port
Address 8~15: address bus 8~15
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 6: I/O port
Address 16~23: address bus 16~23
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 70: Output port (initialized to “1”
output)
Read: Strobe signal, which reads the
external memory.
Develops no strobe signal when not
accessing to the external memory.
Initialized to this function in the external
ROM type, TMP94C251A.
Port 71: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D0 ~ D7
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
Port 72: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D8 ~ D15
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
Port 73: Output port (initialized to “1”
output)
Port 74: Output port (initialized to “1”
output)
Port 75: I/O port
Bus request: Signal, which requests to set
the memory interface terminal to high
impedance.
The following terminals become high
impedance. But the state does not change
while functioning as port.
A0~A23, D0~D15, RD, WRLL, WRLH,
CS0~CS5, OE0~OE1, WE0~WE1, RAS
group, CAS group
Port 76: Output port (initialized to “1”
output)
Bus Acknowledge: Signal, which indicates
that BUSRQ request is received.
Port 80: Output port (initialized to “1”
output)
Chip select 0: Develops “L” level when the
address is within the assigned address
area.
Name
P00~P07
D0~D7
P10~P17
D8~D15
P40~P47
A0~A7
P50~P57
A8~A15
P60~P67
A16~A23
P70
RD
P71
WRL
P72
WRH
P73
P74
P75
BUSRQ
P76
BUSAK
P80
CS0