Toshiba SD-1300A, Service Manual

Page: 66 / 93

3-24
Table 3-5-4 TMP94C251AF(Z) (2/5)
Pin
No.
59
58
57
56
55
29
49
50
51
52
53
44
45
Function
Port 81: Output (initialized to “1” output)
Chip select 1: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 0: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 82: Output port (initialized to “1”
output)
Chip select 2: Develops “L” level when the
address is within the assigned address
area.
Port 83: Output port (initialized to “1”
output)
Chip select 3: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 1: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 84: Output port (initialized to “1”
output)
Chip select 4: Develops “L” level when the
address is within the assigned address
area.
Port 85: Output port (initialized to “1”
output)
Chip select 5: Develops “L” level when the
address is within the assigned address
area.
Port 86: I/O port
Wait: Bus wait request signal
Port A0: Output port (initialized to “1”
output)
Column address strobe 0: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 0: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A1: Output port (initialized to “1”
output)
Upper column address strobe 0: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A2: Output port (initialized to “1”
output)
Out enable 0: Develops out enable signal
for DRAM.
Port A3: Output port (initialized to “1”
output)
Out enable 1: Develops out enable signal
for DRAM.
Port A4: Output port (initialized to “1”
output)
Write enable 0: Develops write enable
signal for DRAM.
Port B0: Output port (initialized to “1”
output)
Column address strobe 1: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 1: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port B1: Output port (initialized to “1”
output)
Upper column address strobe 1: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Name
P81
CS1
RAS0
P82
CS2
P83
CS3
RAS1
P84
CS4
P85
CS5
P86
WAIT
PA0
CAS0
LCAS0
PA1
UCAS0
PA2
OE0
PA3
OE1
PA4
WE0
PB0
CAS1
LCAS1
PB1
UCAS1
Table 3-5-4 TMP94C251AF(Z) (3/5)
Pin
No.
46
47
48
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
Function
Port B2: Output port (initialized to “1”
output)
Port B3: Output port (initialized to “1”
output)
Port B4: Output port (initialized to “1”
output)
Write enable 1: Develops write enable
signal for DRAM.
Port C0: I/O port
Timer output 1: Develops 8 bit timer 0 or
timer 1.
Timer output 7: Develops 16 bit timer 7.
Port C1: I/O port
Timer output 3: Develops 8 bit timer 2 or
timer 3.
Timer output B: Develops 16 bit timer B.
Port D0: I/O port
Timer output 4: Develops 16 bit timer 4.
Port D1: I/O port
Timer input 4: Enters 16 bit timer 4.
Interrupt request terminal 4: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port D2: I/O port
Timer input 5: Enters 16 bit timer 4.
Interrupt request terminal 5: Terminal for
interrupt request signal at the rising edge.
Port D4: I/O port
Timer output 6: Enters 16 bit timer 6.
Port D5: I/O port
Timer input 6: Enters 16 bit timer 6.
Interrupt request terminal 6: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port D6: I/O port
Timer input 7: Enters 16 bit timer 6.
Interrupt request terminal 7: Terminal for
interrupt request signal at the rising edge.
Port E0: I/O port
Timer output 8: Enters 16 bit timer 8.
Port E1: I/O port
Timer input 8: Enters 16 bit timer 8.
Interrupt request terminal 8: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port E2: I/O port
Timer input 9: Enters 16 bit timer 8.
Interrupt request terminal 9: Terminal for
interrupt request signal at the rising edge.
Port E4: I/O port
Timer output A: Develops 16 bit timer A.
Port E5: I/O port
Timer input A: Enters 16 bit timer A.
Interrupt request terminal A: Terminal for
Interrupt request signal of which rising/
falling edge is programmable.
Port E6: I/O port
Timer input B: Enters 16 bit timer A.
Interrupt request terminal B: Terminal for
interrupt request signal at the rising edge.
Port F0: I/O port
Serial transmission data 0 (open drain
output is possible)
Port F1: I/O port
Serial reception data 0
Port F2: I/O port
Serial transmission is possible 0
Serial clock I/O 0
Name
PB2
PB3
PB4
WE1
PC0
TO1
TO7
PC1
TO3
TOB
PD0
TO4
PD1
TI4
INT4
PD2
TI5
INT5
PD4
TO6
PD5
TI6
INT6
PD6
TI7
INT7
PE0
TO8
PE1
TI8
INT8
PE2
TI9
INT9
PE4
TOA
PE5
TIA
INTA
PE6
TIB
INTB
PF0
TXD0
PF1
RXD0
PF2
CTS0
SCLK0