⎯
12
⎯
6 F 2 S 0 8 2 8
2.2.2 Characteristic of Current Differential Element DIF
The differential elements DIF have a percentage restraining characteristic with weak restraint in
the small current region and strong restraint in the large current region, to cope with CT saturation.
The DIF elements have dual percentage restraint characteristics. Figure 2.2.2.1 shows the
characteristics on the differential current (Id) and restraining current (Ir) plane. Id is the vector
summation of the phase current of all terminals and Ir is the scalar summation of the phase current
of all terminals.
Large current region
Ir
B
Id
0
A
5/6 DIFI1
−
2
×
DIFI2
Small current region
Operating
Zone
Figure 2.2.2.1 DIF Element (Ir-Id Plane)
Characteristic A of the DIF element is expressed by the following equation:
Id
≥
(1/6)Ir + (5/6)DIFI1
where DIFI1 is a setting and defines the minimum internal fault current.
This characteristic has weaker restraint and ensures sensitivity to low-level faults.
Characteristic B is expressed by the following equation:
Id
≥
Ir - 2
×
DIFI2
where DIFI2 is a setting and its physical meaning is described later.
This characteristic has stronger restraint and prevents the element from operating falsely in
response to the erroneous differential current which is caused by saturation or transient errors of
the CT during an external fault. If the CT saturation occurs at the external fault in a small current
region of the characteristics and continues, the element may operate falsely caused by increasing
the erroneous differential current. The DIF prevents the false operation by enhancing the
restraining quantity for the DIF calculation, depending on the magnitude of restraining current in
the large current region characteristic B.
The figure shows how the operation sensitivity varies depending on the restraining current.
The same characteristic can be represented on the outflowing current (Iout) and infeeding current
(Iin) plane as shown in Figure 2.2.2.2.
Summary of Contents for GRL150-100 Series
Page 149: ... 148 6 F 2 S 0 8 2 8 ...
Page 154: ... 153 6 F 2 S 0 8 2 8 Appendix B Signal List ...
Page 180: ... 179 6 F 2 S 0 8 2 8 Appendix C Binary Output Default Setting List ...
Page 182: ... 181 6 F 2 S 0 8 2 8 Appendix D Details of Relay Menu ...
Page 195: ... 194 6 F 2 S 0 8 2 8 ...
Page 196: ... 195 6 F 2 S 0 8 2 8 Appendix E Case Outline ...
Page 199: ... 198 6 F 2 S 0 8 2 8 ...
Page 200: ... 199 6 F 2 S 0 8 2 8 Appendix F Typical External Connections ...
Page 223: ... 222 6 F 2 S 0 8 2 8 ...
Page 228: ... 227 6 F 2 S 0 8 2 8 Appendix I Return Repair Form ...
Page 232: ... 231 6 F 2 S 0 8 2 8 Appendix J Technical Data ...
Page 238: ... 237 6 F 2 S 0 8 2 8 Appendix K Symbols Used in Scheme Logic ...
Page 241: ... 240 6 F 2 S 0 8 2 8 ...
Page 242: ... 241 6 F 2 S 0 8 2 8 Appendix L Inverse Time Characteristics ...
Page 248: ... 247 6 F 2 S 0 8 2 8 Appendix M IEC60870 5 103 Interoperability ...
Page 260: ... 259 6 F 2 S 0 8 2 8 Appendix N Resistor Box Option ...
Page 263: ... 262 6 F 2 S 0 8 2 8 ...
Page 264: ... 263 6 F 2 S 0 8 2 8 Appendix O Ordering ...
Page 267: ......