⎯
105
⎯
6 F 2 S 0 8 2 8
Setting the SEF protection for model 120 and 420
The settings for the SEF protection are as follows:
•
Select "SEF" on the "Scheme sw" screen to display the "SEF" screen.
/ 7 S E F
S E 1 E N 1 _
O f f / O n
M S E 1 C - I E C 0
N I / V I / E I / L T I
M S E 1 C - I E E E 0
M I / V I / E I
M S E 1 C - U S 0
C O 2 / C O 8
S E 1 R 0
D E F / D E P
S E 1 S 2 0
O f f / O n
S E 2 E N 0
O f f / O n
S E 3 E N 0
O f f / O n
S E 4 E N 0
O f f / O n
<
SE
∗
EN
>
•
Enter 1(=On) to enable the SEF
∗
and press the ENTER key. If disabling the SEF
∗
, enter
0(=Off) and press the ENTER key.
<
MSE1C
>
To set the SEF1 Inverse Curve Type, do the following.
•
If [MSE1] is 1(=IEC), enter 0(=NI) or 1(=VI) or 2(=EI) or 3(=LTI) and press the ENTER
key.
•
If [MSE1] is 2(=IEEE), enter 0(=MI) or 1(=VI) or 2(=EI) and press the ENTER key.
•
If [MSE1] is 3(=US), enter 0(=CO2) or 1(=CO8) and press the ENTER key.
<
SE1R
>
To set the Reset Characteristic, do the following.
•
If [MSE1] is 2(=IEEE) or 3(=US), enter 0(=DEF) or 1(=DEP) and press the ENTER key.
<
SE1S2
>
To set the Stage 2 Timer Enable, do the following.
•
Enter 1(=On) to enable the SE1S2 and press the ENTER key. If disabling the SE1S2, enter
0(=Off) and press the ENTER key.
•
After setting, press the END key to display the following confirmation screen.
C h a n g e s e t t i n g s ?
Summary of Contents for GRL150-100 Series
Page 149: ... 148 6 F 2 S 0 8 2 8 ...
Page 154: ... 153 6 F 2 S 0 8 2 8 Appendix B Signal List ...
Page 180: ... 179 6 F 2 S 0 8 2 8 Appendix C Binary Output Default Setting List ...
Page 182: ... 181 6 F 2 S 0 8 2 8 Appendix D Details of Relay Menu ...
Page 195: ... 194 6 F 2 S 0 8 2 8 ...
Page 196: ... 195 6 F 2 S 0 8 2 8 Appendix E Case Outline ...
Page 199: ... 198 6 F 2 S 0 8 2 8 ...
Page 200: ... 199 6 F 2 S 0 8 2 8 Appendix F Typical External Connections ...
Page 223: ... 222 6 F 2 S 0 8 2 8 ...
Page 228: ... 227 6 F 2 S 0 8 2 8 Appendix I Return Repair Form ...
Page 232: ... 231 6 F 2 S 0 8 2 8 Appendix J Technical Data ...
Page 238: ... 237 6 F 2 S 0 8 2 8 Appendix K Symbols Used in Scheme Logic ...
Page 241: ... 240 6 F 2 S 0 8 2 8 ...
Page 242: ... 241 6 F 2 S 0 8 2 8 Appendix L Inverse Time Characteristics ...
Page 248: ... 247 6 F 2 S 0 8 2 8 Appendix M IEC60870 5 103 Interoperability ...
Page 260: ... 259 6 F 2 S 0 8 2 8 Appendix N Resistor Box Option ...
Page 263: ... 262 6 F 2 S 0 8 2 8 ...
Page 264: ... 263 6 F 2 S 0 8 2 8 Appendix O Ordering ...
Page 267: ......