⎯
115
⎯
6 F 2 S 0 8 2 8
•
F u n c t i o n s
Setting the logic gate type and timer
•
Select "Logic/Reset" to display the "Logic/Reset" screen.
/ 4 L o g i c / R e s e t
L o g i c 0 _
O R / A N D
R e s e t 0
I n s / D l / D w / L a t
•
Enter 0(=OR) or 1(=AND) to use an OR gate or AND gate and press the ENTER key.
•
Enter 0(=Instantaneous) or 1(=Delayed) or 2(=Dwell) or 3(=Latched) to select the reset timing
and press the ENTER key.
•
Press
the END key to return to the "BO
∗
" screen.
Note:
To release the latch state, push the [RESET] key for more than 3 seconds.
Assigning signals
•
Select "Functions" on the "BO
∗
" screen to display the "Functions" screen.
/ 4 F u n c t i o n s
I n # 1
2 1 _
I n # 2
1 1
I n # 3
2 4
I n # 4
0
T B O s
0 . 2 0
•
Assign signals to gates (In #1 to #4) by entering the number corresponding to each signal
referring to Appendix C. Do not assign the signal numbers 546 to 550 (signal names: "BO1
OP" to "BO5 OP"). And set the delay time of timer TBO.
Note:
If signals are not assigned to all the gates #1 to #4, enter 0 for the unassigned gate(s).
Repeat this process for the outputs to be configured.
4.2.6.10 LEDs
Three LEDs of the GRL150 are user-configurable. A configurable LED can be programmed to
indicate the OR combination of a maximum of 4 elements, the individual statuses of which can be
viewed on the LED screen as “Virtual LEDs.” The signals listed in Appendix B can be assigned to
each LED as follows.
CAUTION
When having changed the LED settings, must release the latch state on a digest screen by
pressing the RESET key for more than 3 seconds.
Summary of Contents for GRL150-100 Series
Page 149: ... 148 6 F 2 S 0 8 2 8 ...
Page 154: ... 153 6 F 2 S 0 8 2 8 Appendix B Signal List ...
Page 180: ... 179 6 F 2 S 0 8 2 8 Appendix C Binary Output Default Setting List ...
Page 182: ... 181 6 F 2 S 0 8 2 8 Appendix D Details of Relay Menu ...
Page 195: ... 194 6 F 2 S 0 8 2 8 ...
Page 196: ... 195 6 F 2 S 0 8 2 8 Appendix E Case Outline ...
Page 199: ... 198 6 F 2 S 0 8 2 8 ...
Page 200: ... 199 6 F 2 S 0 8 2 8 Appendix F Typical External Connections ...
Page 223: ... 222 6 F 2 S 0 8 2 8 ...
Page 228: ... 227 6 F 2 S 0 8 2 8 Appendix I Return Repair Form ...
Page 232: ... 231 6 F 2 S 0 8 2 8 Appendix J Technical Data ...
Page 238: ... 237 6 F 2 S 0 8 2 8 Appendix K Symbols Used in Scheme Logic ...
Page 241: ... 240 6 F 2 S 0 8 2 8 ...
Page 242: ... 241 6 F 2 S 0 8 2 8 Appendix L Inverse Time Characteristics ...
Page 248: ... 247 6 F 2 S 0 8 2 8 Appendix M IEC60870 5 103 Interoperability ...
Page 260: ... 259 6 F 2 S 0 8 2 8 Appendix N Resistor Box Option ...
Page 263: ... 262 6 F 2 S 0 8 2 8 ...
Page 264: ... 263 6 F 2 S 0 8 2 8 Appendix O Ordering ...
Page 267: ......