Mar. 1999 © TOSHIBA TEC
12 - 9
6570/5570 DEVELOPER UNIT
[C] Control signals
(1) DEVCK signal (LGC
→
DEV-MOT:input)
This signal is a reference clock signal for the developer motor to rotate at a fixed speed. The fre-
quency of the reference clock is 821.2Hz.
When the cycle of FG pulse deviation from the reference frequency is within ±6.25%, this state is
specified as lock range (normal rotation). Also, at this time, the LED “LP1” light comes ON.
(2) DEVON signal (LGC
→
DEV-MOT: input)
This signal is the motor ON/OFF control signal. When it becomes “L” level, the motor rotates.
Signal level of motor circuit
Signal
“H” level
“L” level
DEVCK
Reference clock (821.2Hz)
DEVON
Motor OFF
Motor ON
Summary of Contents for 4580
Page 1: ...SERVICE MANUAL DIGITAL PLAIN PAPER COPIER 8070 6570 5570 4580 ...
Page 231: ...6570 5570 DEVELOPER UNIT 12 28 Mar 1999 TOSHIBA TEC 3 Draw out the toner filter ...
Page 252: ...8070 6570 5570 4580 FUSER UNIT 14 6A Mar 1999 TOSHIBA TEC ...
Page 369: ...8070 6570 5570 4580 ADF 16 78 Mar 2000 TOSHIBA TEC 16 13 PC Board 1 PWA F LGC 794 ...
Page 370: ...Mar 2000 TOSHIBA TEC 16 79 8070 6570 5570 4580 ADF 2 PWA F SEN 794 ...
Page 374: ...Mar 1999 TOSHIBA TEC 18 1 6570 5570 PC BOARD 18 PC BOARD 1 PWA F SYS 300 ...
Page 375: ...6570 5570 PC BOARD 18 2 Mar 1999 TOSHIBA TEC 2 PWA F MTB 300 ...
Page 376: ...Mar 1999 TOSHIBA TEC 18 3 6570 5570 PC BOARD 3 PWA F LGC 300 ...
Page 377: ...6570 5570 PC BOARD 18 4 Mar 1999 TOSHIBA TEC 5 PWA F MOT 300 4 PWA F ADU 300 ...
Page 378: ...Mar 1999 TOSHIBA TEC 18 5 6570 5570 PC BOARD 6 PWA F SLG 300 7 PWA F SDV 300 ...
Page 379: ...6570 5570 PC BOARD 18 6 Mar 1999 TOSHIBA TEC 8 PWA F PLG 300 ...