Rev 0.2 / Jan. 2008
10
1
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
CLE
ALE
CE
WE
RE
WP
MODE
H
L
L
Rising
H
X
Read Mode
Command Input
L
H
L
Rising
H
X
Address Input(5 cycles)
H
L
L
Rising
H
H
Write Mode
Command Input
L
H
L
Rising
H
H
Address Input(5 cycles)
L
L
L
Rising
H
H
Data Input
L
L
L
(1)
H
Falling
X
Sequential Read and Data Output
L
L
L
H
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/Vcc
Stand By
Table 6: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
