texet TF-127 Service Manual Download | Manualshive

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B.Power

B.Power

INV_EN

H. LCD Backlight control

H. LCD Backlight control

INV_EN

I2C_SCL

I2C_SDA

I Rtc

I Rtc

I2C_SCL

I2C_SDA

DM1

ID1

DP1

VBUS1

ID1

F. Usb

F. Usb

DM1

ID1

DP1

VBUS1

ID1

ASCLK

ALRCLK

AMCLK

ADATA0/AL

MUTE

SHOT ON/FF

J Audio

J Audio

ASCLK

ALRCLK

AMCLK

ADATA0/AL

MUTE

SHOT ON/FF

PWM

CKV

OEV

D_CLK

STHL

OEH

STVL

LCD_R[5..0]

LCD_G[5..0]

LCD_B[5..0]

VCOM

G. LCD TCON and LCD power

G. LCD TCON and LCD power

PWM

CKV

OEV

D_CLK

STHL

OEH

STVL

LCD_R[5..0]

LCD_G[5..0]

LCD_B[5..0]

VCOM

SD/MS_CLK

SD/MS_CMD

SD/MS_CLK

SD/MS_CMD

SD/MS_CMD

SD/MS_CLK

XD_D0

XD_D1

XD_D5/SD_D1

SD/XD_WP

XD_CLE_CLE

XD_D3/SD_CLK

XD_RB_RB

XD_ALE_ALE

XD_D6/SD_D2

XD_D2/SD_CMD

XD_RE_RE

SD/MS/XD_IN

XD_D7/SD_D3

XD_CE_CE

XD_WE_WE

CARD_EN

XD_D4/SD_D0

E. Card

E. Card

SD/MS_CLK

SD/MS_CMD

SD/MS_CLK

SD/MS_CMD

SD/MS_CMD

SD/MS_CLK

XD_D0

XD_D1

XD_D5/SD_D1

SD/XD_WP

XD_CLE_CLE

XD_D3/SD_CLK

XD_RB_RB

XD_ALE_ALE

XD_D6/SD_D2

XD_D2/SD_CMD

XD_RE_RE

SD/MS/XD_IN

XD_D7/SD_D3

XD_CE_CE

XD_WE_WE

CARD_EN

XD_D4/SD_D0

NAND_CLE

NAND_ALE

NAND_nWE

M1_BA0

M1_A[11..0]

M1_CAS_N

M1_DQM1

M1_A[11..0]

NAND_R/B

NAND_RE

RESET_N

NAND_CE

M1_D[7..0]

F_nCS

M1_D[15..8]

M1_DQM0

M1_RAS_N

M1_WE_N

M1_D[7..0]

F_nOE

M1_DQM1

M1_D[15..8]

M1_SCS0_N

M1_DQM0

M1_WE_N

M1_CLK

M1_BA0

M1_D[15..8]

M1_DQM1

M1_BA1

M1_A[11..0]

M1_DQM0

M1_D[7..0]

D. Memory

D. Memory

NAND_CLE

NAND_ALE

NAND_nWE

M1_BA0

M1_A[11..0]

M1_CAS_N

M1_DQM1

M1_A[11..0]

NAND_R/B

NAND_RE

RESET_N

NAND_CE

M1_D[7..0]

F_nCS

M1_D[15..8]

M1_DQM0

M1_RAS_N

M1_WE_N

M1_D[7..0]

F_nOE

M1_DQM1

M1_D[15..8]

M1_SCS0_N

M1_DQM0

M1_WE_N

M1_CLK

M1_BA0

M1_D[15..8]

M1_DQM1

M1_BA1

M1_A[11..0]

M1_DQM0

M1_D[7..0]

M1_D[15..8]

XD_D2/SD_CMD

XD_D3/SD_CLK

XD_D4/SD_D0

XD_D5/SD_D1

XD_D6/SD_D2

XD_D7/SD_D3

PWM

NAND_CE

ADATA0/AL

ALRCLK

ASCLK

AMCLK

NAND_RE

F_nCS

F_nOE

NAND_ALE

D_CLK

OEV

STHL

I2C_SCL

I2C_SDA

NAND_CLE

NAND_nWE

LCD_R[5..0]

NAND_R/B

LCD_G[5..0]

LCD_B[5..0]

SD/MS/XD_IN

SD/XD_WP

CARD_EN

CKV

VCOM

OEH

DP1

ID1

DM1

VBUS1

STVL

M1_CLK

M1_DQM1

M1_D[7..0]

M1_A[11..0]

M1_CAS_N

M1_WE_N

M1_SCS0_N

M1_RAS_N

M1_DQM0

M1_BA0

INV_EN

RESET_N

M1_BA1

XD_D1

XD_D0

XD_WE_WE

XD_RE_RE

XD_RB_RB

XD_CE_CE

SD/MS/XD_IN

XD_ALE_ALE

XD_CLE_CLE

MUTE

STVR SW

C. Decoder

C. Decoder

M1_D[15..8]

XD_D2/SD_CMD

XD_D3/SD_CLK

XD_D4/SD_D0

XD_D5/SD_D1

XD_D6/SD_D2

XD_D7/SD_D3

PWM

NAND_CE

ADATA0/AL

ALRCLK

ASCLK

AMCLK

NAND_RE

F_nCS

F_nOE

NAND_ALE

D_CLK

OEV

STHL

I2C_SCL

I2C_SDA

NAND_CLE

NAND_nWE

LCD_R[5..0]

NAND_R/B

LCD_G[5..0]

LCD_B[5..0]

SD/MS/XD_IN

SD/XD_WP

CARD_EN

CKV

VCOM

OEH

DP1

ID1

DM1

VBUS1

STVL

M1_CLK

M1_DQM1

M1_D[7..0]

M1_A[11..0]

M1_CAS_N

M1_WE_N

M1_SCS0_N

M1_RAS_N

M1_DQM0

M1_BA0

INV_EN

RESET_N

M1_BA1

XD_D1

XD_D0

XD_WE_WE

XD_RE_RE

XD_RB_RB

XD_CE_CE

SD/MS/XD_IN

XD_ALE_ALE

XD_CLE_CLE

MUTE

STVR SW

Ver01

2 of 12

Checked by:

Approved by:

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Summary of Contents for TF-127

Page 1: ...SERVICE MANUAL Premier confidential...

Page 2: ...210DP Internal Panel 128MB SDRAM 2MB NOR FLASH 256Mb Nand FLASH 7 Analog TFT LCD panels Interfaces 4 in 1 card reader MS SDHC MMC XD USB 2 0 Host Port 6 buttons 1 2009 06 01 REVISION HISTORY REV Revis...

Page 3: ...N M1_DQM0 M1_WE_N M1_CLK M1_BA0 M1_D 15 8 M1_DQM1 M1_BA1 M1_A 11 0 M1_DQM0 M1_D 7 0 D Memory D Memory NAND_CLE NAND_ALE NAND_nWE M1_BA0 M1_A 11 0 M1_CAS_N M1_DQM1 M1_A 11 0 NAND_R B NAND_RE RESET_N NA...

Page 4: ...CON6 dc_power C18 0 1UF 1 2 3 Q3 3904 C121 0 1uF C119 0 1uF C27 0 1uF FB29 FB FB27 FB C115 0 1uF NC R1 43k 1 NC C118 10uf 16V R76 100K R74 10k 1 NC EC127 100uf 10V R77 20K EC24 220uf 16V FB11 FB C22...

Page 5: ...S3 5 2A C160 1uf 25v FB17 FB FB 3 OV 5 SW 1 GND 2 EN 4 IN 6 U19 MP3202DJ R180 0R R183 4 7K EC159 100uf 10V L801 FB 50R L800 FB 50R D22 SS14 L11 10uH C125 0 1uF R184 0 47 BL_VCC INV_GND INV_GND INV_GND...

Page 6: ...ize A4 f o t e e h S 9 0 0 2 n u J 0 1 e t a D I2C_SCL I2C_SDA 1 2 Y2 32 768KHz D23 1N4148 R43 0 C108 GC5 5V 0 22F R44 0 X1 1 X2 2 VBAT 3 GND 4 SDA 5 SCL 6 IRQ FOUT 7 VDD 8 U7 ISL1208 C55 0 1uF AGND D...

Page 7: ...uF FB20 FB R373 2 2K 1 2 3 Q34 MMBT3904 5V 1 D 2 D 3 ID 4 GND 5 SHLD 6 GND 7 GND 8 GND 9 CON13 MiniUSB R106 0 EC110 100uf 10V FB19 FB120 C95 0 1uF AGND AGND USB5V AGND AGND AGND AGND AGND USB5V Core3...

Page 8: ...K R73 4 7K 1 2 J108 SPEAKER C189 1UF R540 10K R539 10K R372 0R R30 0 EC386 100uf 10V R803 100K R802 100K EC28 100uF 10V 4C3 680p 4R2 1K SDATA 1 SCLK 2 LRCLK 3 MCLK 4 AOUTR 5 AGND 6 VA 7 AOUTL 8 U410 C...

Page 9: ...48 B2 13 49 B1 12 50 B0 11 51 R L 10 52 V1 9 53 V4 8 54 V7 7 55 V10 6 56 V12 5 57 V13 4 58 10V 3 59 GND7 2 60 VCOM2 1 GND 31 GND 32 CON9 AT080TN03_2 R150 68 C101 10uF 25V R148 68 R144 150 R165 680 1 P...

Page 10: ...4 XD_CLE 5 XD_ALE 6 XD_WE 7 XD_WP IN 8 XD_GND 9 XD_D0 10 XD_D1 11 XD_D2 12 XD_D3 13 XD_D4 14 XD_D5 15 XD_D6 16 XD_D7 17 XD_VCC 18 XD_GND 19 GND1 20 GND2 21 NC 22 SD CD 23 SD DATA2 24 MS GND 25 SD DATA...

Page 11: ...RP2 4 22R 1 MAK2 C86 0 1uF C58 0 1uF C76 0 1uF EC60 100uf 10V R52 NC R53 NC C62 0 1uF 1 MAK1 R50 4 7K C84 0 1uF DQ0 2 DQ1 3 DQ2 5 DQ3 6 DQ4 8 DQ5 9 DQ6 11 DQ7 12 DQ8 39 DQ9 40 DQ10 42 DQ11 43 DQ12 45...

Page 12: ...TCON_STV2 11 TCON_STH1 6 TCON_STH2 5 TCON_OEH 14 TCON_VCOM 13 JTAG_TMS I2C_MASTER_CLOCK 141 JTAG_TDI I2C_MASTER_DATA 142 JTAG_TCK MUTE 143 JTAG_TDO OTG_VBUS 144 LCD_R0 121 LCD_R1 122 LCD_R2 123 LCD_R...

Page 13: ...V70 R40 200 SW5 RETURN SW2 up SW3 down 1 3 2 D7 BAV70 1 3 2 D6 BAV70 SW6 ENTER SW4 left AGND AGND AGND 1 2 3 4 J1 4 HEADER AGND K1 K2 K3 K706ADV10 Ver01 12 of 12 Checked by Approved by KEY_IR_Usb SCH...

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Page 24: ...LCD MODULE SPECIFICATION Customer Model Name AT070TN82 SPEC NO A070 82 TT 01 Date 2008 07 22 Version 01 Preliminary Specification Final Specification For Customer s Acceptance Approved by Comment App...

Page 25: ...pyright belongs to InnoLux Any unauthorized use is prohibited InnoLux copyright 2004 All rights reserved Copying forbidden Record of Revision Version Revise Date Page Content Pre spec 01 2008 07 22 In...

Page 26: ...Conditions 7 3 2 1 Current Consumption 8 3 2 2 Backlight Driving Conditions 8 3 3 Power Sequence 9 3 4 Timing Characteristics 10 3 4 1 Timing Conditions 10 3 4 2 Timing Diagram 12 4 Optical Specifica...

Page 27: ...lement a Si TFT active matrix 3 Resolution 800 3 RGB 480 4 Display mode Normally white Transmissive 5 Dot pitch 0 0635 W 0 1905 H mm 6 Active area 152 4 W 91 44 H mm 7 Module size 165 W 104 H 5 5 D mm...

Page 28: ...rtical start pulse input when U D H Note 1 3 OEV I Output enable 4 CKV I Vertical clock 5 STVU I O Vertical start pulse input when U D L Note 1 6 GND P Power Ground 7 EDGSL I Select rising edge or fal...

Page 29: ...a 29 R0 I Red data LSB 30 GND P Power Ground 31 GND P Power Ground 32 G5 I Green data MSB 33 G4 I Green data 34 G3 I Green data 35 G2 I Green data 36 G1 I Green data 37 G0 I Green data LSB 38 STHL I O...

Page 30: ...4 V7 I Gamma voltage level 7 55 V10 I Gamma voltage level 10 56 V12 I Gamma voltage level 12 57 V13 I Gamma voltage level 13 58 AVDD P Power for Analog Circuit 59 GND P Power Ground 60 VCOM I Common v...

Page 31: ...ote 3 When REV L it s under normal operation When REV H these data will be inverted 2 2 Backlight Unit Section LED Light Bar Connector is used for the integral backlight system The recommended model i...

Page 32: ...V14 0 3 0 6AVDD V Operation Temperature TOP 30 85 Storage Temperature TST 30 85 LED Reverse Voltage Vr 1 2 V Each LED Note 3 LED Forward Current IF 25 mA Each LED Note 1 AVDD 0 1 V1 V2 V3 V4 V5 V6 V7...

Page 33: ...ower voltage VGL 7 7 7 0 6 3 V VCOM 4 1 V V1 V14 2 5 2V V1 V7 0 4 AVDD AVDD 0 1 V Input signal voltage V8 V14 0 1 0 6 AVDD V Input logic high voltage VIH 0 7 DVDD DVDD V Input logic low voltage VIL 0...

Page 34: ...DD 40 0 50 0 mA AVDD 10 4V 3 2 2 Backlight Driving Conditions Values Item Symbol Min Typ Max Unit Remark Voltage for LED Backlight VL 9 3 9 9 10 5 V Note1 Current for LED Backlight IL 170 180 200 mA L...

Page 35: ...22 Page 9 27 The copyright belongs to InnoLux Any unauthorized use is prohibited 3 3 Power Sequence 1 Power on 2 Power off Note Data include DCLK POL OEV CKV STVU STVD STHL STHR LD R0 R5 G0 G5 B0 B5 D...

Page 36: ...time Tsu 4 ns Data hold time Thd 2 ns Time that the last data to LD Tld 1 Tcph Pulse width of LD Twld 2 Tcph Time that LD to STHL R Tlds 5 Tcph POL set up time Tpsu 6 ns POL hold time Tphd 6 ns CKV f...

Page 37: ...gs to InnoLux Any unauthorized use is prohibited Output rise time Ttlh 500 1000 ns Output falling time Tthl 400 800 ns OEV pulse width Twcl 1 us OEV to Driver output delay time Toe 900 ns Horizontal l...

Page 38: ...Any unauthorized use is prohibited 3 4 2 Timing Diagram Tsu Thd Tcw Tcw Tsu Thd First data Second data Last data Tphl Tphl 70 30 70 70 30 30 70 70 70 70 70 800 799 2 1 DCLK STHL R input STHR L output...

Page 39: ...ght belongs to InnoLux Any unauthorized use is prohibited Tsu Thd Tcw Tcw Tsu Thd First data Second data Last data Tsu Thd Tphl Tphl 70 30 70 30 30 70 30 70 30 30 70 70 70 70 70 70 400 399 2 1 DCLK ST...

Page 40: ...Lux Any unauthorized use is prohibited DCLK LD STHL R input LD POL Odd outputs Even outputs 70 Last Tld 70 Twld 70 Tlds 70 70 70 70 30 70 30 Tpsu Tphd TpsuTphd High Z Tst 10 90 High Z Tst 90 10 70 Tps...

Page 41: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 15 27 The copyright belongs to InnoLux Any unauthorized use is prohibited Hs DCLK RGB 1 2 3 800 799 798 DE Tdh Th Fig 3 4 Horizontal timing 2...

Page 42: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 16 27 The copyright belongs to InnoLux Any unauthorized use is prohibited Fig 3 5 Vertical shift clock timing...

Page 43: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 17 27 The copyright belongs to InnoLux Any unauthorized use is prohibited Fig 3 6 Vertical timing from up to down...

Page 44: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 18 27 The copyright belongs to InnoLux Any unauthorized use is prohibited RGB 1 2 3 480 479 478 DE Vs Tvd Tv Fig 3 7 Vertical timing...

Page 45: ...T 90 12 o clock 40 50 Viewing angle CR 10 B 270 6 o clock 60 70 degree Note 1 TON 10 20 msec Note 3 Response time TOFF 15 30 msec Note 3 Contrast ratio CR 400 500 Note 4 WX 0 26 0 31 0 36 Color chroma...

Page 46: ...should be measured in dark room After 30 minutes operation the optical properties are measured at the center point of the LCD screen Response time is measured by Photo detector TOPCON BM 7 other items...

Page 47: ...time between photo detector output intensity changed from 10 to 90 Fig 4 3 Definition of response time Note 4 Definition of contrast ratio state Black the on LCD when measured Luminance state White th...

Page 48: ...ided into 9 measuring areas Refer to Fig 4 4 Every measuring point is placed at the center of each measuring area max min B B Yu Uniformity Luminance L Active area length W Active area width W W 3 W 3...

Page 49: ...m Sweep 10Hz 55Hz 10Hz 2 hours for each direction of X Y Z 6 hours for total Mechanical Shock 100G 6ms X Y Z 3 times for each direction Package Vibration Test Random Vibration 0 015G G Hz from 5 200HZ...

Page 50: ...mponents 5 Put cover board such as acrylic board on the surface of LCD panel to protect panel from damages 6 Transparent electrodes may be disconnected if you use the LCD panel under environmental con...

Page 51: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 25 27 The copyright belongs to InnoLux Any unauthorized use is prohibited 7 Mechanical Drawing...

Page 52: ...AT070TN82 165 104 5 5 TBD 50pcs 2 Partition BC Corrugated Paper 512 349 226 1 466 1 set 3 Corrugated Bar BC Corrugated Paper 512 162 0 046 4 set 4 Corrugated Board BC Corrugated Paper 510 343 0 130 1...

Page 53: ...INNOLUX SPEC NO A070 82 TT 01 Date 2008 07 22 Page 27 27 The copyright belongs to InnoLux Any unauthorized use is prohibited 8 3 Packaging Drawing...

Page 54: ...L 6210DP A V Processor User s Guide AMLOGIC Inc 3930 Freedom Circle Santa Clara CA 95054 U S A www amlogic com AMLOGIC reserves the right to change any information described herein at any time without...

Page 55: ...AUDIO INTERFACES 13 3 4 DISPLAY OUTPUT INTERFACES 14 3 4 1 Digital Output 14 3 4 2 LCD Timing Controller 14 3 5 PERIPHERALS 15 3 5 1 Card Reader Interface 15 3 5 2 USB Interface 15 4 OPERATING CONDITI...

Page 56: ...ocessor User Guide Version 0 2 5 19 2008 3 24 AMLOGIC Proprietary Revision History Revision Number Revised Date By Changes 0 1 2008 3 3 bwester Initial release 0 2 2008 3 3 Bwester Fix some errors in...

Page 57: ...ons Contrast enhancement hue adjustment video scaling video interpolation and zoom are also supported The high resolution scalar supports both up scaling and down scaling of images and video The scala...

Page 58: ...FF and other popular picture formats o Supports zoom in and out rotation and transition effects Special Trick Modes o Pause o Reverse playback o Multiple steps fast forward backward Picture Processing...

Page 59: ...system on each memory card Core CPU Sub system o 32 bit core CPU dedicated for user applications o Embedded debug interface using ICE JTAG o Shared MPEG SDRAM as run time data storage for minimal sys...

Page 60: ...m1_we_n This pin controls the Boot Option after RESET Tie to 3 3v with 10k resistor if the boot device is NAND FLASH Tie to ground with a 10k resistor if the boot device is NOR FLASH m1_dqm1 This pin...

Page 61: ...ocessor User Guide Version 0 2 5 19 2008 8 24 AMLOGIC Proprietary Powe On Configuration Logic SDRAM 1Mx16 8 bit Flash FLASH ControllerSDRAM Controller GND reset_n Power Applied t0 m1_we_n M1_ GND m1_d...

Page 62: ...epicts a typical crystal circuit the actual values of the components depend on the type of crystal used in the application OSCIN OSCOUT 22pF OSCIN OSCOUT NC 27Mhz 100k XTAL 22pF 27 MHz 3 1 3 JTAG for...

Page 63: ...over all possible external devices or system level signals numerous general purpose I O pins are available on the chip for purpose like Portable Media Player keypads Each GPIO pin can be independently...

Page 64: ...0 10 BA1 BA0 CLK RAS CAS CS DQML DQMH WE 4M x 16 SDRAM 3 2 2 FLASH Interface The FLASH interface can accommodate an 8 bits FLASH device Due to the limited number of I O pins the FLASH interface is sh...

Page 65: ...IC Proprietary very large capacity that ranges from 32MB to more than 1GB The NAND FLASH should be connected as indicated in the following diagram R B RE CE WE CLE ALE DQ 7 0 NAND_R nB NAND_nRE NAND_C...

Page 66: ...sigma algorithm is used to improve the performance and ensure high SNR output The implementation includes a multi tap interpolation filter which increases the sample rate of the audio channels to the...

Page 67: ...d before the data is sent to the digital output 3 4 2 LCD Timing Controller The AML6210DP AV processor has a built in LCD timing controller TCON that works in conjunction with the digital output to pr...

Page 68: ...sum and transferring data to from SDRAM The hardware provides interface for the necessary signals e g SD_CLK SD_CMD SD_D0 3 for SD cards but signals like card detect and write protect are provided usi...

Page 69: ...evel input current 10nA 1 Ioz Tri state output leakage current 10nA 1 uA PD Power Dissipation Vin VDD 0 8 W 4 2 Absolute Maximum Ratings The table below gives the absolute maximum ratings Exposure to...

Page 70: ...ulse I O 12 VSS33 Digital Ground Digital Ground P 13 TCON_VCOM LCD Panel signal LCD panel clock pulse I O 14 TCON_OEH LCD Panel signal LCD panel clock pulse I O 15 TCON_CPH1 LCD Panel signal LCD panel...

Page 71: ...2V P 51 M1_D_9 M1_D_9 SDRAM1 and or FLASH I O 52 M1_D_10 M1_D_10 SDRAM1 and or FLASH I O 53 M1_D_11 M1_D_11 SDRAM1 and or FLASH I O 54 M1_D_12 M1_D_12 SDRAM1 and or FLASH I O 55 VDD33 I O Power 3 3V D...

Page 72: ...A core AP 84 PLLC_AVDD33 PLL VDD PLL power AP 85 PLLC_AVSS33 PLL Ground PLL ground AP 86 PLLB_AVDD33 PLL VDD PLL power AP 87 PLLB_AVSS33 PLL Ground PLL ground AP 88 PLLA_AVDD33 PLL VDD PLL power AP 89...

Page 73: ...l Output O 123 LCD_R2 LCD Video Out LCD Video Signal Output O 124 LCD_R3 LCD Video Out LCD Video Signal Output O 125 LCD_R4 LCD Video Out LCD Video Signal Output O 126 LCD_R5 LCD Video Out LCD Video S...

Page 74: ...15 94 BUTTON2 GPIO 16 93 BUTTON1 GPIO 17 92 VDD12 GPIO 18 91 OSCOUT NAND_WE_n 19 90 OSCIN NAND_RDYBSY 20 89 PLLA_AVSS33 NAND_CE_n 21 88 PLLA_AVDD33 NAND_RD_n 22 87 PLLB_AVSS33 VDD12 23 86 PLLB_AVDD33...

Page 75: ...IO_28 7 TCON_OEV1 TCON_OEV1 LCD_GPIO_24 8 TCON_CPV1 TCON_CPV1 LCD_GPIO_25 10 TCON_STV1 TCON_STV1 LCD_GPIO_26 11 TCON_STV2 TCON_STV2 LCD_GPIO_27 13 TCON_VCOM TCON_VCOM LCD_GPIO_31 14 TCON_OEH TCON_OEH...

Page 76: ...QM0 FLASH_A_20 8 M1_SCS0_n M1_SCS0_n 9 M1_RAS_n M1_RAS_n FLASH_A_22 10 M1_CAS_n M1_CAS_n 11 M1_WE_n M1_WE_n FLASH_WE_n 12 M1_D_8 M1_D_8 NAND_8 FLASH_A_12 15 M1_D_9 M1_D_9 NAND_9 ASH_A_13 FL 16 M1_D_10...

Page 77: ...sor User Guide Version 0 2 5 19 2008 24 24 AMLOGIC Proprietary 6 Mechanical Specifications The AML6210DP A V processor is packaged using a 144 pins LQFP package The mechanical dimensions are given in...

Page 78: ...and is subject to change without notice Hynix does not assume any responsibility for use of circuits described No patent licenses are implied Rev 0 2 Jan 2008 1 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8...

Page 79: ...le 2Gbit 256Mx8bit NAND Flash Memory Revision History Revision No History Draft Date Remark 0 0 Initial Draft Jul 03 2007 Preliminary 0 1 1 Add ULGA Package Figures texts are added 2 Change tRCBSY to...

Page 80: ...block download without latency time FAST BLOCK ERASE Block erase time 1 5ms typ Multi block erase time 2 blocks 1 5ms typ CACHE READ Internal 2048 64 Byte buffer to improve the read throughtput STATU...

Page 81: ...ignals the status of the device during each operation In a system with multiple mem ories the R B pins can be connected all together to provide a global status signal The copy back function allows the...

Page 82: ...gram 9 966 3 5 2 a 2 2 a 2 2QO 5 IO15 IO8 Data Input Outputs x16 only IO7 IO0 Data Input Outputs CLE Command latch enable ALE Address latch enable CE Chip Enable RE Read Enable WE Write Enable WP Writ...

Page 83: ...9VV 1 1 ODVK 7623 1 1 1 1 1 1 5 5 1 1 9FF 9VV 1 1 3 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 9FF 9VV 1 1 1 2 2 2 2 1 1 1 1 1 1 ODVK 7623 Figure 2 48TSOP1 Contact x8 and x16 Device 1 1 1 1 1 1 1 1 9VV 9VV 9VV...

Page 84: ...Y27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash 1 1 1 1 1 1 1 1 1 1 1 1 3 966 2 2 2 2 2 2 2 966 2 5 1 1 1 1 1 1 1 1 1 966 966 9 9 1 5 1 1 1 1 1 1 1 1 1 0 1 Figure 4 52 ULGA Contactions x8 Device To...

Page 85: ...the rise edge of WE RE READ ENABLE The RE input is the serial data out control and when active drives the data onto the I O bus Data is valid tREA after the falling edge of RE which also increments t...

Page 86: ...PGM 85h 10h MULTI PLANE PROGRAM 80h 11h 81h 10h MULTI PLANE COPYBACK PROGRAM 85h 11h 81h 10h BLOCK ERASE 60h D0h MULTI PLANE BLOCK ERASE 60h 60h D0h READ STATUS REGISTER 70h Yes RANDOM DATA INPUT 85h...

Page 87: ...H H Write Mode Command Input L H L Rising H H Address Input 5 cycles L L L Rising H H Data Input L L L 1 H Falling X Sequential Read and Data Output L L L H H X During Read Busy X X X X X H During Pr...

Page 88: ...starts a modify ing operation write erase the Write Protect pin must be high See Figure 7 and Table 13 for details of the timings requirements Addresses are always applied on IO7 0 regardless of the b...

Page 89: ...loading period in which up to 2112bytes of data may be loaded into the data register followed by a non volatile programming period where the loaded data is programmed into the appropriate cell The ser...

Page 90: ...ter will be set Device supports pass fail status of each plane Figure 21 details the sequence 3 4 Block Erase The Erase operation is done on a block basis Block address loading is accomplished in ther...

Page 91: ...e using random data input command 85h as shown in Figure19 Copy back program operation is allowed only within same plane 3 7 Multi Plane Copy Back Program The copy back program is configured to quickl...

Page 92: ...atus Register definitions The command register remains in Status Read mode until further commands are issued to it Therefore if the status register is read during a random data output the read command...

Page 93: ...nter an address to retrieve the next sequential page is read When the Cache Read function is issued SR 6 is cleared to zero busy After the operation is begun SR 6 is set to one ready and the host may...

Page 94: ...Figure 28 The two step command sequence for program erase provides additional software protection 4 2 Ready Busy The device has a Ready Busy output that provides method of indicating the completion o...

Page 95: ...t or Output Voltage 0 6 to 4 6 V Vcc Supply Voltage 0 6 to 4 6 V Table 8 Absolute maximum ratings NOTE 1 Except for the rating Operating Temperature Range stresses above those listed in the Table Abso...

Page 96: ...9 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash Figure 5 Block Diagram 5 66 5 67 5 2817 5 352 5 0 5 6 21752 5 9 1 5 7 21 200 1 17 5 2 200 1 5 67 5 7 5 67 5 2 5 8 56 2 5 3 8 5 2 5 0ELW 0ELW 1 1...

Page 97: ...uA Input Leakage Current ILI VIN 0 to Vcc max 10 uA Output Leakage Current ILO VOUT 0 to Vcc max 10 uA Input High Voltage VIH 0 8xVcc Vcc 0 3 V Input Low Voltage VIL 0 3 0 2xVcc V Output High Voltage...

Page 98: ...10 pF Table 11 Pin Capacitance TA 25C F 1 0MHz Parameter Symbol Min Typ Max Unit Program Time Multi Plane Program Time tPROG 200 700 us Dummy Busy Time for Two Plane Program tDBSY 0 5 1 us Number of p...

Page 99: ...B 100 ns Read Cycle Time tRC 25 ns RE Access Time tREA 20 ns RE High to Output High Z tRHZ 100 ns CE High to Output High Z tCHZ 50 ns CE High to Output hold tCOH 15 ns RE High to Output Hold tRHOH 15...

Page 100: ...ode 2nd cycle Device Code 3rd cycle 4th cycle 5th cycle HY27UF082G2B 3 3V x8 ADh DAh 10h 95h 44h HY27UF162G2B 3 3V x16 ADh CAh 10h D5h 44h Table 16 Read ID Data Table IO Page Program Block Erase Read...

Page 101: ...t Spare Area 64K 128K 256K 512KB 0 0 0 1 1 0 1 1 Organization X8 X16 0 1 Table 18 4th Byte of Device Identifier Description Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Die Package 1 2 4 8 0 0 0 1 1 0...

Page 102: ...lash Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Plane Number 1 2 4 8 0 0 0 1 1 0 1 1 Plane Size w o redundant Area 64Mb 0 0 0 128Mb 0 0 1 256Mb 0 1 0 512Mb 0 1 1 1Gb 1 0 0 2Gb 1 0 1 4Gb 1 1 0 8Gb 1 1...

Page 103: ...DC units x8 Table 21 Page organization in EDC units x16 IO Copy back Program CODING 0 Pass Fail Pass 0 Fail 1 1 EDC status NO error 0 2 EDC Validity Invalid 0 Valid 1 3 NA 4 NA 5 Ready Busy Busy 0 Rea...

Page 104: ...256Mx8bit NAND Flash Figure 6 Command Latch Cycle W 6 W 6 W 3 RPPDQG 2 W W 6 W 6 W W W W 6 W 6 W W 6 W 6 W 6 W 6 W 6 W W W W W W W W W 3 W 3 W W 3 W 3 W W W W 6 RO GG 2 RO GG 5RZ GG 5RZ GG 5RZ GG W 6...

Page 105: ...Rev 0 2 Jan 2008 28 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash W W W W 3 W 1RWHV 1 ILQDO PHDQV WHV 1 1 ILQDO W W W W W 6 W 6 W 6 W 3 W 3 2 W 6 Figure 8 Input Data Latch Cycle...

Page 106: ...5 2 LV YDOLG ZKHQ IUHTXHQF LV KLJKHU WKDQ 0 W5 2 VWDUWV WR EH YDOLG ZKHQ IUHTXHQF LV ORZHU WKDQ 0 Figure 10 Sequential Out Cycle after Read EDO Type CLE L WE H ALE L W5 5 2 5 W5 W55 RXW RXW RXW 1RWHV...

Page 107: ...ND Flash Figure 11 Status Read Cycle W 6 W 5 W W 6 W W 3 W 5 W 5 W 6 W5 W W 2 W5 W5 2 K 6WDWXV 2XWSXW W W 5 2 5 2 5 5 W W 5 W55 K K RO GG ROXPQ GGUHVV 5RZ GGUHVV RO GG 5RZ GG 5RZ GG 5RZ GG XV RXW 1 RX...

Page 108: ...08 31 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash W W 5 W W 2 W5 W5 W55 XV K K RXW 1 RXW 1 RXW 1 RO GG RO GG 5RZ GG 5RZ GG 5RZ GG ROXPQ GGUHVV 5RZ GGUHVV 5 2 5 Figure 13 Read1 Operation inte...

Page 109: ...08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash 5 5 2 W 5 K ROXPQ GGUHVV 5RZ GGUHVV XV K K K RXW 1 RXW 0 RXW 1 RXW 0 RO GG 5RZ GG 5RZ GG 5RZ GG RO GG ROXPQ GGUHVV RO GG RO GG W5 W5 W W 5 W55 W 5 W5 W5 F...

Page 110: ...6 W5 6 W5 6 K RO GG RO GG 5RZ GG 5RZ GG 5RZ GG K K K DWD DFKH 3DJH XIIHU HOO UUD K RXW 1 RXW 0 RXW 0 RXW 1 RXW 1 RXW 1 K RXW 0 RXW 1 RXW 1 RXW 0 RXW 1 RXW 1 W5 5 5 2 3DJH 1 3DJH 1 3DJH 1 3DJH 1 3DJH 1...

Page 111: ...K RO GG 6HULDO DWD QSXW RPPDQG ROXPQ GGUHVV 127 6 W LV WKH WLPH IURP WKH ULVLQJ HGJH RI ILQDO DGGUHVV F FOH WR WKH ULVLQJ HGJH RI ILUVW GDWD F FOH 5RZ GGUHVV 5HDG 6WDWXV RPPDQG 3URJUDP RPPDQG 2 6XFFHV...

Page 112: ...RO GG RO GG 5ZR GG 5ZR GG 5ZR GG W W W 5 W352 6HULDO DWD QSXW RPPDQG 5DQGRP DWD QSXW RPPDQG ROXPQ GGUHVV ROXPQ GGUHVV 5RZ GGUHVV 127 6 W LV WKH WLPH IURP WKH ULVLQJ HGJH RI ILQDO DGGUHVV F FOH WR WKH...

Page 113: ...K 5HDG FRPPDQG ROXPQ DGGUHVV ROXPQ DGGUHVV SDJH URZ DGGUHVV UURU FRUUHFWLRQ GDWD LQSXW RS EDFN 3URJUDP FRPPDQG 3DJH URZ DGGUHVV 5HDG FRQILUP RPPDQG K K DWD 1 DWD 1 DWD 0 DWD 0 K K 2 RO DGG RO DGG 5RZ...

Page 114: ...ULVLQJ HGJH RI ILUVW GDWD F FOH ROXPQ GGUHVV ROXPQ GGUHVV 5RZ GGUHVV 5RZ GGUHVV 5HDO 6WDWXV RPPDQG XV 2 6XFHVVIXO 3URJUDP 2 UURU LQ 3URJUDP RS DFN DWD QSXW RPPDQG RO GG 5RZ GG 5RZ GG 5RZ GG RO GG RO...

Page 115: ...B Series 2Gbit 256Mx8bit NAND Flash W 5 2 5 W W 56 86 K 2 5RZ GG 5RZ GG 5RZ GG K XWR ORFN UDVH 6HWXS RPPDQG UDVH RPPDQG 5HDG 6WDWXV RPPDQG 2 6XFFHVVIXO UDVH 2 UURU LQ UDVH 3DJH 5RZ GGUHVV K Figure 20...

Page 116: ...a 9DOLG a L HG RZ L HG RZ a L HG RZ a 9DOLG a 9DOLG L HG LJK a 9DOLG 1RWH Q FRPPDQG EHWZHHQ K DQG K LV SURKLEWHG H FHSW K DQG W 6 W352 6HULDO DWD QSXW RPPDQG ROXPQ GGUHVV 3DJH 5RZ GGUHVV XS WR WH DWD...

Page 117: ...PPDQG ORFN UDVH 6HWXS RPPDQG UDVH RQILUP RPPDQG 5HDG 6WDWXV RPPDQG 2 6XFFHVVIXO UDVH 2 UURU LQ UDVH XV 5RZ GGUHVV GGUHVV 5HVWULFWLRQ IRU 7ZR 3ODQH ORFN UDVH 2SHUDWLRQ 5 5 2 5 2 a W K K 5RZ GG 5RZ GG a...

Page 118: ...K K RO DGG RO DGG 5RZ DGG 5RZ DGG 5RZ DGG RO DGG LQ 1 LQ 0 RO DGG 5RZ DGG 5RZ DGG 5RZ DGG K K RO DGG LQ 1 LQ 0 RO DGG 5RZ DGG 5RZ DGG 5RZ DGG K K K RO DGG RO DGG 5RZ DGG 5RZ DGG 5RZ DGG K DGGUHVV K K...

Page 119: ...Rev 0 2 Jan 2008 42 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash K 5 2 K W5 5HDG RPPDQG GGUHVV F FOH 0DNHU RGH HYLFH RGH K WK FOH WK FOH UG FOH K K K K W 5 Figure 24 Read ID Operation...

Page 120: ...rface Using CE don t care To simplify system interface CE signal is ignored during data loading or sequential data reading as shown below So it is possible to connect NAND Flash to a microprocessor Th...

Page 121: ...s 2Gbit 256Mx8bit NAND Flash 9 9 9 9 9 X VPD QYDOLG 9 9 9 2SHUDWLRQ PV PD 9 3 5HDG XV GRQ W FDUH GRQ W FDUH GRQ W FDUH Figure 27 Reset Operation K W567 5 2 5 Figure 28 Power On and Data Protection Tim...

Page 122: ...W FXUUHQWV RI DOO GHYLFHV WLHG WR WKH 5 SLQ 5S PD LV GHWHUPLQHG E PD LPXP SHUPLVVLEOH OLPLW RI WU 9FF 9 7D S LJ 5S YV WU WI 5S YV LEXV 9FF 0D 92 0D 9 P 2 5S LEXV 5S RKP LEXV LEXV WU WI V WI XV 5HDG 9F...

Page 123: ...2Gbit 256Mx8bit NAND Flash Figure 30 page programming within a block kh hGpuGaGk GOXP k GO P k GO P k G w G Z w G Z w GZX w GY w GX w GW O P a OZYP a OZP OYP OXP l UPGy G G GOw P kh hGpuGaGk GOXP k G...

Page 124: ...vices are supplied with all the locations inside valid blocks erased FFh The Bad Block Information is written prior to shipping Any block where the 1st Byte in the spare area of the 1st or 2nd th page...

Page 125: ...data in other pages in the same block the block can be replaced by re programming the cur rent data and copying the rest of the replaced block to an available valid block Refer to Table 23 and Figure...

Page 126: ...D Flash Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low tWW 100ns min The operations are enabled and disabled as follows Figure 33 36 W K K 2 3 5 K K...

Page 127: ...Rev 0 2 Jan 2008 50 1 HY27UF 08 16 2G2B Series 2Gbit 256Mx8bit NAND Flash K W K 2 3 5 K W K 2 3 5 Figure 35 Enable Erasing Figure 36 Disable Erasing...

Page 128: ...12 x 20mm Package Mechanical Data Symbol millimeters Min Typ Max A 1 200 A1 0 050 0 150 A2 0 980 1 030 B 0 170 0 250 C 0 100 0 200 CP 0 100 D 11 910 12 000 12 120 E 19 900 20 000 20 100 E1 18 300 18...

Page 129: ...0 30 0 35 A2 0 55 0 60 0 65 b 0 40 0 45 0 50 D 8 90 9 00 9 10 D1 4 00 D2 7 20 E 10 90 11 00 11 10 E1 5 60 E2 8 80 e 0 80 FD 2 50 FD1 0 90 FE 2 70 FE1 1 10 SD 0 40 SE 0 40 Figure 38 63 ball FBGA 9 x 1...

Page 130: ...Typ Max A 16 90 17 00 17 10 A1 13 00 A2 12 00 B 11 90 12 00 12 10 B1 10 00 B2 6 00 C 1 00 C1 1 50 C2 2 00 D 1 00 D1 1 00 E 0 65 CP1 0 65 0 70 0 75 CP2 0 95 1 00 1 05 Figure 39 52 ULGA 12 x 17mm Packa...

Page 131: ...Version x Package Type x Package Material x Operating Tem perature x Bad Block Y Year ex 5 year 2005 6 year 2006 w w W ork W eek ex 12 work week 12 xx Process Code N ote Capital Letter Sm all Letter...

Page 132: ...ment Pagers PDA POS Equipment Test Meters Fixtures Office Automation Copiers Fax Home Appliances Computer Products Other Industrial Medical Automotive Ordering Information PART NUMBER MARKING VDD RANG...

Page 133: ...ier and is intended to be connected to one pin of an external 32 768kHz quartz crystal 3 VBAT This input provides a backup supply voltage to the device VBAT supplies power to the device in the event t...

Page 134: ...A IDD2 Supply Current With I2C Active VDD 5V 40 120 A 1 2 IDD3 Supply Current Low Power Mode VDD 5V LPMODE 1 1 4 5 A 1 IBAT Battery Supply Current VBAT 3V 400 950 nA 1 ILI Input Leakage Current on SC...

Page 135: ...ossing 30 of VDD 100 ns tHD DAT Input data hold time From SCL falling edge crossing 30 of VDD to SDA entering the 30 to 70 of VDD window 0 900 ns tSU STO STOP condition setup time From SCL rising edge...

Page 136: ...INPUT TIMING SDA OUTPUT TIMING tF tLOW tBUF tAA tR WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will chang...

Page 137: ...9 600E 9 800E 9 1E 6 40 20 0 20 40 60 80 TEMPERATURE C I BAT A 1 0E 06 1 2E 06 1 4E 06 1 6E 06 1 8E 06 2 0E 06 2 2E 06 2 4E 06 40 20 0 20 40 60 80 TEMPERATURE C I DD1 A VCC 5V VCC 3 3V 400 0E 9 600 0...

Page 138: ...ice in the event that the VDD supply fails This pin can be connected to a battery a Super Cap or tied to ground if not used IRQ FOUT Interrupt Output Frequency Output This dual function pin can be use...

Page 139: ...VDD to drop below VTRIP Since the additional monitoring of VDD vs VTRIP is no longer needed that circuitry is shut down and less power is used while operating from VDD Power savings are typically 600...

Page 140: ...frequency output mode is set by using the FO bits to select 15 possible output frequency values from 0 to 32kHz The frequency output can be enabled disabled during battery backup mode using the FOBAT...

Page 141: ...ng into the control and status alarm and user SRAM registers TABLE 1 REGISTER MEMORY MAP ADDR SECTION REG NAME BIT RANGE DEFAULT 7 6 5 4 3 2 1 0 00h RTC SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 59 00...

Page 142: ...hether VDD or VBAT is applied first The loss of only one of the supplies does not set the RTCF bit to 1 The first valid write to the RTC section after a complete power failure resets the RTCF bit to 0...

Page 143: ...M MODE BIT IM This bit enables disables the interrupt mode of the alarm function When the IM bit is set to 1 the alarm will operate in the interrupt mode where an active low pulse width of 250ms will...

Page 144: ...the RTC registers As the RTC advances the alarm will be triggered once a match occurs between the alarm registers and the RTC registers Any one alarm register multiple registers or all registers can b...

Page 145: ...during SCL LOW periods SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions See Figure 12 On power up of the ISL1208 the SDA pin is in the input mode All I2C interf...

Page 146: ...operation The master must respond with an ACK after receiving a Data Byte of a read operation FIGURE 12 VALID DATA CHANGES START AND STOP CONDITIONS FIGURE 13 ACKNOWLEDGE RESPONSE FROM RECEIVER FIGURE...

Page 147: ...ndition After each of the three bytes the ISL1208 responds with an ACK At this time the I2C interface enters a standby state Read Operation A Read operation consists of a three byte instruction follow...

Page 148: ...n with good accuracy In addition to the analog compensation afforded by the adjustable load capacitance a digital compensation feature is available for the ISL1208 There are 3 bits known as the Digita...

Page 149: ...locking Add a ground trace around the crystal with one end terminated at the chip ground This will provide termination for emitted noise in the vicinity of the RTC device In addition it is a good idea...

Page 150: ...quation for IBAT vs VBAT is Using this equation to solve for the average current given 2 voltage points gives Combining with Equation 2 gives the equation for backup time where CBAT 0 47F VBAT2 4 7V V...

Page 151: ...032 0 81 0 007 0 18 0 005 0 13 0 008 0 20 0 004 0 10 0 0216 0 55 7 Typ R 0 014 0 36 0 118 0 002 3 00 0 05 0 012 0 006 0 002 0 30 0 15 0 05 0 0256 0 65 Typ 8 Lead Miniature Small Outline Gull Wing Pac...

Page 152: ...l or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent...

Page 153: ...8 x16 CMOS SDRAM Rev 1 2 August 2004 Samsung Electronics reserves the right to change products or specification without notice 128Mb F die SDRAM Specification Revision 1 2 August 2004 54 TSOP II with...

Page 154: ...Mb F die x4 x8 x16 CMOS SDRAM Rev 1 2 August 2004 Revision History Revision 1 0 January 2004 First release Revision 1 1 May 2004 Added Note 5 sentense of tRDL parameter Revision 1 2 August 2004 Correc...

Page 155: ...ting frequencies programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications JEDEC standard 3 3V...

Page 156: ...5 0 020 0 50 0 005 0 001 0 003 0 125 0 035 0 075 0 400 10 16 0 45 0 75 0 018 0 030 0 010 0 25 TYP 0 8 C 54 28 1 27 0 004 0 10 MAX 0 028 0 71 0 012 0 30 0 0315 0 80 0 047 1 20 MAX 0 039 1 00 0 004 0 10...

Page 157: ...er Latency Burst Length Programming Register Address Register Row Buffer Refresh Counter Row Decoder Col Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE L U DQM LWE LDQM DQi CLK ADD LCA...

Page 158: ...e Latches row addresses on the positive going edge of the CLK with RAS low Enables row access precharge CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CA...

Page 159: ...rating conditions Voltage referenced to VSS 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD VDDQ 3 0 3 3 3 6 V Input logic high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input logic lo...

Page 160: ...0ns 20 mA ICC2NS CKE VIH min CLK VIL max tCC Input signals are stable 10 Active standby current in power down mode ICC3P CKE VIL max tCC 10ns 5 mA ICC3PS CKE CLK VIL max tCC 5 Active standby current i...

Page 161: ...g 20ns 20 mA ICC2NS CKE VIH min CLK VIL max tCC Input signals are stable 10 Active standby current in power down mode ICC3P CKE VIL max tCC 10ns 5 mA ICC3PS CKE CLK VIL max tCC 5 Active standby curren...

Page 162: ...recharge time tRP min 18 20 ns 1 Row active time tRAS min 42 45 ns 1 tRAS max 100 us Row cycle time tRC min 60 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 5 Last data in to Active delay tDA...

Page 163: ...respect to VSS Notes 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr tf 1ns...

Page 164: ...wn Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min V I mA I mA I mA 0 0 0 0 0 0 0 0 0 4 27 5 70 2 17 7 0 65 41 8 107 5 26 9 0 85 51 6 133 8 33 3 1 0 58 0 151 2 37 6 1 4 70 7 187 7 46 6 1 5 72 9...

Page 165: ...06 1 8 7 35 2 0 9 83 2 2 12 48 2 4 15 30 2 6 18 31 VSS Clamp CLK CKE CS DQM DQ VSS V I mA 2 6 57 23 2 4 45 77 2 2 38 26 2 0 31 22 1 8 24 58 1 6 18 37 1 4 12 56 1 2 7 57 1 0 3 37 0 9 1 75 0 8 0 58 0 7...

Page 166: ...harge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto A...

Page 167: ...Each Manufacturing Company This datasheet has been downloaded from www EEworld com cn Free Download Daily Updated Database 100 Free Datasheet Search Site 100 Free IC Replacement Search Site Convenien...

Page 168: ...me control and SE headphone vol Maximum Volume Setting for SE Mode ume control Notebook and pocket PCs benefit from Adjustable SE Volume Control the integrated feature set that minimizes external Refe...

Page 169: ...150 C Tstg Storage temperature range 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent da...

Page 170: ...3 0 5 6 SHUTDOWN 2 V VDD 5 V PVDD SE BTL 0 V IDD Supply current max power into a 3 load SHUTDOWN 2 V RL 3 1 5 ARMS PO 2 W stereo IDD SD Supply current shutdown mode SHUTDOWN 0 0 V 1 20 A TA 25 C VDD P...

Page 171: ...Right channel headphone input selected when HP LINE is held high ROUT 2 O Right channel negative audio output ROUT 24 O Right channel positive audio output SHUTDOWN 15 I Places the amplifier in shutdo...

Page 172: ...ROUT PVDD PGND VDD BYPASS AGND LOUT LOUT RLINEIN RIN HP LINE VOLUME SEDIFF SEMAX FADE _ HP LINE _ _ BYP _ BYP BYP EN SE BTL L MUX _ HP LINE _ _ BYP _ BYP BYP EN SE BTL SE BTL LHPIN LLINEIN LIN TPA601...

Page 173: ...1 12 1 16 26 1 23 1 27 24 1 35 1 38 22 1 46 1 49 20 1 57 1 60 18 1 68 1 72 16 1 79 1 83 14 1 91 1 94 12 2 02 2 06 10 2 13 2 17 8 2 25 2 28 6 2 2 36 2 39 4 2 47 2 50 2 2 58 2 61 0 2 70 2 73 2 2 81 2 83...

Page 174: ...1 04 34 1 12 1 16 32 1 23 1 27 30 1 35 1 38 28 1 46 1 49 26 1 57 1 60 24 1 68 1 72 22 1 79 1 83 20 1 91 1 94 18 2 02 2 06 16 2 13 2 17 14 2 25 2 28 12 2 36 2 39 10 2 47 2 50 8 2 58 2 61 6 2 2 70 2 73...

Page 175: ...rmonic distortion plus noise BTL vs Output power 6 7 8 vs Frequency 4 5 THD N Total harmonic distortion plus noise SE vs Output power 9 vs Output voltage 10 Closed loop response 11 12 vs Temperature 1...

Page 176: ...5 1 2 5 20 20 k 50 100 200 500 1 k 2 k 5 k 10 k f Frequency Hz THD N Total Harmonic Distortion Noise SE VO 1 VRMS VDD 5 V RL 10 k Gain 14 dB SE PO Output Power W THD N Total Harmonic Distortion Noise...

Page 177: ...5 1 2 5 0 500 m 1 1 5 2 VO Output Voltage rms THD N Total Harmonic Distortion Noise SE 1 kHz 20 kHz 20 Hz VDD 5 V RL 10 k Gain 14 dB SE 10 0 01 0 02 0 05 0 1 0 2 0 5 1 2 5 10 m 200 m 50 m 100 m PO Out...

Page 178: ...ain 20 dB f Frequency Hz Closed Loop Gain dB Phase Degrees 0 1 2 3 4 5 6 7 8 9 10 40 25 5 20 35 50 65 95 10 110 125 Supply Current mA TA Free Air Temperature C I DD VDD 5 V Mode BTL SHUTDOWN VDD 80 1...

Page 179: ...0 8 1 1 2 1 4 1 6 1 8 2 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 PO Output Power W Power Dissipation PER CHANNEL W P D VDD 5 V BTL 4 8 3 0 20 40 60 80 100 120 140 160 180 200 0 100 150 200 250 300 50 8...

Page 180: ...2 120 0 110 100 90 80 70 60 50 40 30 20 10 20 20 k 100 1 k 10 k f Frequency Hz Crosstalk dB Left to Right Right to Left VDD 5 V PO 1 W RL 8 Gain 0dB BTL 120 0 110 100 90 80 70 60 50 40 30 20 10 20 20...

Page 181: ...RL 8 BTL 20 20 k 100 1 k 10 k f Frequency Hz PSRR Power Supply Rejection Ratio SE dB 100 0 90 80 70 60 50 40 30 20 10 Gain 14 dB Gain 0 dB VDD 5 V RL 32 C BYP 0 47 F SE 0 10 20 30 40 50 60 70 80 90 4...

Page 182: ...utput Noise Voltage 120 140 10 k 20 k 180 40 0 60 160 V n V RMS Gain 0 dB VDD 5 V BW 22 Hz to 22 kHz RL 8 BTL Gain 20 dB f Frequency Hz TPA6011A4 SLOS392A FEBRUARY 2002 REVISED JULY 2004 OUTPUT NOISE...

Page 183: ...ower Supply VDD 100 k 100 k CC In From DAC or Potentiometer DC Voltage C BYP System Control CC Right Speaker Left Speaker Headphones 1 k 1 k TPA6011A4 SLOS392A FEBRUARY 2002 REVISED JULY 2004 Figure 2...

Page 184: ...ier Figure 29 Typical TPA6011A4 Application Circuit Using Differential Inputs The ability of the TPA6011A4 to easily switch between BTL and SE modes is one of its most important cost saving features T...

Page 185: ...stereo inputs to the amplifier For design flexibility the HP LINE control is independent of the output mode SE or BTL which is controlled by the aforementioned SE BTL pin To allow the amplifier to sw...

Page 186: ...ss capacitor from the nominal voltage of VDD 2 to ground This time is dependent on the value of the bypass capacitor For a 0 47 F capacitor that is used in the application diagram in Figure 28 the tim...

Page 187: ...e voltage on the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to determine the SE gain Some audio systems require that the gain be limited in the single...

Page 188: ...2 can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing If using a DAC to contro...

Page 189: ...with the corner frequency determined in Equation 2 The value of Ci is important to consider as it directly affects the bass low frequency performance of the circuit Consider the example where Ri is 7...

Page 190: ...to the output drive signal This noise is from the midrail generation circuit internal to the amplifier which appears as degraded PSRR and THD N Bypass capacitor C BYP values of 0 47 F to 1 F ceramic o...

Page 191: ...of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor Figure 36 shows a Class AB audio power amplifier APA in a...

Page 192: ...ded Configuration and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation The increased dissipation is understandable considering that the BTL...

Page 193: ...veform is a half wave rectified shape whereas in BTL it is a full wave rectified waveform This means RMS conversion factors are different Keep in mind that for most of the waveform both the push and p...

Page 194: ...to pass the loudest portions of the signal without distortion In other words music typically has a crest factor between 12 dB and 15 dB When determining the optimal ambient operating temperature the i...

Page 195: ...formula for a 3 load The maximum ambient temperature depends on the heat sinking ability of the PCB system The derating factor for the PWP package is shown in the dissipation rating table Use equatio...

Page 196: ...heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC The exposed thermal pad dimensions for this package are shown in the following illustra...

Page 197: ......

Page 198: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 199: ...inal regulator with 800mA output current capability The output voltage is adjustable with the use of a resistor divider For fixed output voltage versions the output voltage is internally set at 2 85V...

Page 200: ...T VIEW 1 ADJ GND 2 VOUT TAB 3 VIN FRONT VIEW 1 ADJ GND 2 VOUT TAB 3 VIN AIC1117CT TO 220 AIC1117CY SOT 223 2 3 1 2 3 1 FRONT VIEW 1 ADJ GND 2 VOUT TAB 3 VIN AIC1117CM TO 263 n ABSOLUTE MAXIMUM RATINS...

Page 201: ...15 0 2 Line Regulation 0 C TJ 125 C 0 035 0 2 Load Regulation TJ 25 C IO 10 800mA 0 C TJ 125 C 0 1 0 2 0 3 0 4 Dropout Voltage VOUT VREF 1 10mA IO 800mA 0 C TJ 125 C 1 2 1 4 V Current Limit 0 C TJ 125...

Page 202: ...V Line Transient Response Time S Output Voltage mV AC Input Voltage V 0 10 20 30 40 50 6 0 7 0 100 50 0 50 COUT 10 F Tantalum VOUT 3 3V Dropout Voltage VOUT 3 3V Output Current mA Minimum Differential...

Page 203: ...N Providing VREF 1 25V typ for adjustable VOUT VREF VOUT VADJ and IADJ 55 A typ GND PIN Power ground VOUT PIN Adjustable output voltage VIN PIN Power Input n PHYSICAL DIMENSIONS l TO 220 unit mm SYMBO...

Page 204: ...28 TYP H 9 40 10 42 E b2 A C1 A1 H D L b e L 0 51 l SOT 223 SYMBOL MIN MAX A1 0 02 0 12 B 0 60 0 80 B1 2 90 3 15 C 0 24 0 35 D 6 30 6 80 E 3 30 3 70 e 2 30 TYP H 6 70 7 30 0 10 13 3 13 3 C 0 91 MIN E...

Page 205: ...AIC1117 7 l TO 263 unit mm SYMBOL MIN MAX A 4 06 4 83 b 0 50 1 00 b2 1 14 1 40 C 0 7 c2 1 14 1 40 D 8 63 9 66 E 9 65 10 29 e 2 54 TYP L 14 60 15 88 L1 2 28 2 80 E L A C L1 e D b2 b C2 L2 L2 1 40...

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