Rev 0.2 / Jan. 2008
9
1
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
L
(1)
L
(1)
L
(1)
L
(1)
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
5th Cycle
A28
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
FUNCTION
1st CYCLE
2nd CYCLE 3rd CYCLE 4th CYCLE
Acceptable command
during busy
READ1
00h
30h
-
-
READ FOR COPY-BACK
00h
35h
-
-
READ ID
90h
-
-
-
RESET
FFh
-
-
-
Yes
PAGE PROGRAM
80h
10h
-
-
COPY BACK PGM
85h
10h
-
-
MULTI PLANE PROGRAM
80h
11h
81h
10h
MULTI PLANE COPYBACK
PROGRAM
85h
11h
81h
10h
BLOCK ERASE
60h
D0h
-
-
MULTI PLANE
BLOCK ERASE
60h
60h
D0h
-
READ STATUS REGISTER
70h
-
-
-
Yes
RANDOM DATA INPUT
85h
-
-
-
RANDOM DATA OUTPUT
05h
E0h
-
-
READ CACHE (RANDOM)
00h
31h
-
-
READ CACHE (SEQUENTIAL)
31h
-
-
-
READ CACHE END
3Fh
-
-
-
READ EDC STATUS REGISTER
7Bh
-
-
-
Table 5: Command Set
Note:
1. READ EDC STATUS REGISTER is only available on Copy Back operation.
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
I/O8-
IO15
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
L
(1)
2nd Cycle
A8
A9
A10
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
3rd Cycle
A11
A12
A13
A14
A15
A16
A17
A18
L
(1)
4th Cycle
A19
A20
A21
A22
A23
A24
A25
A26
L
(1)
5th Cycle
A27
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.