Texas Instruments TLV1544EVM, User Manual

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DSP Interface
4-9 Operation
4.3 DSP Interface
The TLV1544 can also interface with a DSP, from the TMS320 family for exam-
ple, through a serial port. The analog-to-digital converter (ADC) serves as a
slave device where the DSP supplies FS and the serial I/O CLK. Transmit and
receive operations are concurrent. The falling edge of FS must occur no later
than seven I/O CLK periods after the falling edge of CS.
DSP I/O cycles differ from microprocessor I/O cycles in the following ways:
-
When interfaced with a DSP, the output data MSB shows after FS
↓
and
the rest of the output data changes on the rising edge of I/O CLK, and input
data is sampled on the first four falling edges of I/O CLK after FS falling
when INV CLK is high, or the first four rising edges of I/O CLK after FS fal-
ling when INV CLK is low. This operation is the opposite when interfaced
with a microprocessor.
-
A new DSP I/O cycle is started on the rising edge of I/O CLK after the rising
edge of FS. The internal state machine is reset on each falling edge of I/O
CLK when FS is high. This operation is opposite when interfaced with a
microprocessor.
-
The TLV1544 supports a 16-clock cycle when interfaced with a DSP. The
output data is padded with six trailing zeros when it is operated in DSP
mode.