TLV1544 Overview
4-2
Operation
4.1
TLV1544 Overview
The following paragraphs describe the TLV1544 10-bit ADC.
4.1.1
Description
The TLV1544 is a CMOS 10-bit switched-capacitor successive approximation
ADC. Figure 4–1 shows the functional block diagram for the device.
The device has a chip-select (CS), input-output clock (I/O CLK), data input
(DATA IN) and serial data output (DATA OUT). An additional frame sync (FS)
input initiates data transfer when using a DSP and connects to the DSP serial
port FSX pin. INV CLK state allows DSP or SPI
and QSPI
timing.
The CSTART is used for delayed sampling.
Figure 4–1. Functional Block Diagram
Analog
MUX
Self-Test
Reference
Input
Data
Register
Control
Logic
and
I/O
Counters
10-Bit ADC
(Switch Capacitors)
Output Data Register
10-to-1
Data Selector
Sample
and
Hold Function
CLOCK
A0–A3
REF+
REF–
DATA IN
DATA OUT
EOC
FS
CS
CSTART
INV CLK
I/O CLK
Terminals shown are for the DB package.
1–8
14
13
17
16
19
12
15
9
11
18
4.1.2
Timing Diagrams
Figures 4–2 through 4–5 show the system signal timing diagrams. These
timing diagrams show the four basic signal I/O signal sets required for
microprocessor and DSP timing.
Summary of Contents for TLV1544EVM
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Page 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...
Page 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...
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