TLV1544 Overview
4-4
Operation
Figure 4–4. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode,
INV CLK = High)
NOTE A:
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓
before responding to control
input signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
I/O CLK
DI
DO
EOC
CS
(see Note A)
FS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1
2
3
4
5
6
7
8
9
10
ÎÎÎÎÎ
ÎÎÎÎÎ
Ï
Ï
Ï
Ï
Ï
Ï
Sample
MSB
MSB
LS
B
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Hi-Z
A3
A2
A1
A0
Address Sampled
Conversion Starts on 10th I/O CLK
↓
(6 I/O CLKs)
Access
11
12
13
14
15
16
Hold/Conversion
CS Rise After 16th I/O CLK
↓
Initialize Counter
0s
td(EOC
↑
-CS
↓
)
Initialize State Machine
7 I/O CLKs
Maximum
Summary of Contents for TLV1544EVM
Page 2: ...Printed in U S A 08 98 SLAU014...
Page 8: ...vi...
Page 16: ...1 6 Overview...
Page 19: ...PCB Layout 2 3 Physical Description Figure 2 2 PCB Layout...
Page 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...
Page 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...
Page 22: ...PCB Layout 2 6 Physical Description Figure 2 5 PCB Layout...
