Circuit Function
3-4
Circuit Description
Figure 3–2. Generation of AVdd/2 with Buffer for Channel A1 Input Biasing with JP6
Removed
_
+
_
+
10 k
Ω
100 pF
TP15
TP16
TP14
U5
U4B
10 k
Ω
10 k
Ω
{
10 k
Ω
{
AV
DD
To A1 Input
Channel A1
† These components are not part of the TLV1544 EVM and must be added externally.
R
R
C
†
TLE2027
1/2 TLV2432
3.2.4
Unbuffered Analog Inputs
The BNC connectors, J3 and J4, provide two unbuffered inputs which go to the
edge of the breadboard area. These inputs are protected by diodes D5, D6,
D7, and D8 to prevent damage from moderate voltages in excess of the supply
rails. Jumpers JP3 and JP4 are used to directly connect these inputs to ADC
inputs A2 and A3 . Other signal conditioning can be placed in the breadboard
area and those outputs connected to A2 or A3 through an open JP3 or JP4.
R31 and R32 are set to 0 ohms but can be changed to provide additional cur-
rent limit protection.
When using the unbuffered inputs, the driving source impedance must be low
for proper slew rate of the input signal. The source must provide enough
current into 50 pF to arrive at final voltage value within the device specified
sampling time. Also, if the source noise is not below the 10 bit level, this noise
could cause jitter in the least significant bit.
3.2.5
Power
A balanced voltage input of
±
10 volts maximum (
±
7 volts minimum) and
ground should be supplied to the EVM through connector J1 with the plus
supply voltage applied to J1-1, the minus supply to J1-3, and ground to J1-2.
The op amp, U5, uses the bipolar supplies. The rest of the EVM uses regulated
5 volts from the positive supply through the TPS7101 low dropout regulator.
Switch SW1 can switch the output voltage of the regulator from nominally
5-volt to 2.7-volt operation. The regulator output voltage is divided into the
digital supply (DVdd) and analog supply (AVdd) through ferrite beads and
individual filter capacitors. The 5-volt or 2.7-volt output powers U1, U2, U4, U6
and U7.
The
±
7 to
±
10 volts is applied to the TLE2027 while only the plus supply voltage
is also applied to the TPS7101 low-dropout regulator. The TPS7101 regulates
Summary of Contents for TLV1544EVM
Page 2: ...Printed in U S A 08 98 SLAU014...
Page 8: ...vi...
Page 16: ...1 6 Overview...
Page 19: ...PCB Layout 2 3 Physical Description Figure 2 2 PCB Layout...
Page 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...
Page 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...
Page 22: ...PCB Layout 2 6 Physical Description Figure 2 5 PCB Layout...