Texas Instruments TLV1544EVM, User Manual

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I/O Interface Connector Provisions
1-4 Overview
1.5 I/O Interface Connector Provisions
The connector interface is versatile allowing different connection
arrangements depending on the user selected interface. A 12-position single
inline male connector, J5, is hard wired to the input/output signals of the
TLV1544 through the SN74HC244. J6 is a dual row, 24 position header, so any
dual row 100 mil center connector can be used up to 24 pins. J5 and J6 are
separated by a jumper row that allows J6 to be user configured for the
appropriate external interface. The schematic shows the signal arrangement
for J5. Either J5 or J6 can easily be used with the corresponding male ribbon
cable plug.
The two rows of plated-through holes, designated as JPA shorting jumpers,
allow the on board signals to connect externally in a variety of user defined
selections. Using these jumpers, the TLV1544EVM I/O signals can be conve-
niently connected to an existing hardware (DSP EVMs, microprocessor EVM,
micro-controller EVMs, etc.) by appropriate jumper placement.
When using J6, the clock lines should have a ground line on either side in the
ribbon cable to minimize cross-talk. If possible every other conductor in the
ribbon cable should be grounded.
1.6 Timing and Signal Requirements
The signal timing necessary is shown in Chapter 4, Figures 4–2 through 4–5
for the various processor options.