TLV1544 Overview
4-6
Operation
4.1.4
TLV1544 Terminal Functions
Table 4–2 explains the terminal functions for the TLV1544.
Table 4–2. Terminal Functions
Terminal
Name
No.
D
No.
DB
I/O
Description
A0–A3
A4–A7
6–9
–
1–4
5–8
I
Analog inputs. The analog inputs are internally multiplexed. (For a source imped-
ance greater than 1 k
Ω
, the asynchronous start should be used to increase the
sampling time.)
CS
16
15
I
Chip select. A high-to-low transition on CS resets the internal counters and
controls and enables DATA IN, DATA OUT, and I/O CLK within the maximum setup
time. A low-to-high transition disables DATA IN, DATA OUT, and I/O CLK within
the setup time.
CSTART
10
9
I
Sampling/conversion start control. CSTART controls the start of the sampling of
an analog input from a selected multiplex channel. A high-to-low transition starts
the sampling of the analog input signal. A low-to-high transition puts the sample-
and-hold function in hold mode and starts the conversion. CSTART is independent
from I/O CLK and works when CS is high. The low CSTART duration controls the
duration of the sampling cycle for the switched capacitor array. CSTART is tied to
V
CC
if not used.
DATA IN
2
17
I
Serial data input. The 4-bit serial data selects the desired analog input and test
voltage to be converted next in a normal cycle. These bits can also set the
conversion rate and enable the power-down mode. When operating in the micro-
processor mode, the input data is presented MSB first and is shifted in on the first
four rising (INV CLK = V
CC
) or falling (INV CLK = GND) edges of I/O CLK (after
CS
↓
) Wh
ti
i th DSP
d
th i
t d t i
t d MSB fi t
d
CS
↓
). When operating in the DSP mode, the input data is presented MSB first and
is shifted in on the first four falling (INV CLK = V
CC
) or rising (INV CLK = GND)
edges of I/O CLK (after FS
↓
).
After the four input data bits have been read into the input data register, DATA IN
is ignored for the remainder of the current conversion period.
DATA
OUT
1
16
O
3-state serial output of the A/D conversion result. DATA OUT is in the high-
impedance state when CS is high and active when CS is low or after FS
↓
(in DSP
mode). With a valid CS signal, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB or LSB value of the
previous conversion result. DATA OUT changes on the falling (microprocessor
mode) or rising (DSP mode) edge of I/O CLK.
EOC
4
19
O
End of conversion. EOC goes from a high to a low logic level on the tenth rising
(microprocessor mode) or tenth falling (DSP mode) edge of I/O CLK and remains
low until the conversion is complete and data is ready for transfer. EOC can also
indicate that the converter is busy.
FS
13
12
I
DSP frame synchronization input. FS indicates the start of a serial data frame into
or out of the device. FS is tied to V
CC
when interfacing the device with a micropro-
cessor.
GND
11
10
Ground return for internal circuitry. All voltage measurements are with respect to
GND, unless otherwise noted.
INV CLK
12
11
I
Inverted clock input. INV CLK is tied to GND when an inverted I/O CLK is used
as the source of the input clock. This affects both microprocessor and DSP inter-
faces. INV CLK is tied to V
CC
if I/O CLK is not inverted. INV CLK can also invoke
a built-in test mode.
Summary of Contents for TLV1544EVM
Page 2: ...Printed in U S A 08 98 SLAU014...
Page 8: ...vi...
Page 16: ...1 6 Overview...
Page 19: ...PCB Layout 2 3 Physical Description Figure 2 2 PCB Layout...
Page 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...
Page 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...
Page 22: ...PCB Layout 2 6 Physical Description Figure 2 5 PCB Layout...
