THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
See Note A
WE
OE
I/O
Input
Output
Output
Hi-Z
Hi-Z
tw(WP)
td(OEW)
td(WOE)
td(DEN)
tsu
th
td(DZ)
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
See
Note A
NOTE A: All timing measurements are based on 50% of edge transition.
Analog Input
Input Clock
Digital Output
Sample 1
Sample 2
Sample 3
Sample 4
Sample 5
tc
t(CKH)
tw(CKL)
td(o)
Pipeline Latency
Sample 1
Sample 2
Figure 2. Digital Output Timing Diagram
