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THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range: AV

to AGND, DV

to DGND

– 0.3 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND

– 0.3 V to 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

to DV

– 6.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode input voltage range, MODE to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . .

Analog input voltage range, AIN to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range, VREF to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference output voltage range, VREF to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock input voltage range, CLK to AGND

– 0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range, digital input to DGND

– 0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range, digital output to DGND

– 0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

– 65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds

300

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN

NOM

MAX

UNIT

High level input voltage VIH

Clock input

0.8

AVDD

High-level input voltage, VIH

All other inputs

0.8

DVDD

Low-level input voltage VIL

Clock input

0.2

AVDD

Low-level in ut voltage, VIL

All other inputs

0.2

DVDD

analog inputs

MIN

NOM

MAX

UNIT

Analog input voltage, VI(AIN) (PGA = 1x, top, bottom, or external reference mode)

REFBS

REFTS

Reference input voltage, VI(VREF)

Clamp input voltage, VI(CLAMPIN)

0.1

AVDD–0.1

power supply

MIN

NOM

MAX

UNIT

Supply voltage

Maximum sampling rate = 30 MSPS

AVDD

3.3

5.5

Supply voltage

Maximum sampling rate = 30 MSPS

DVDD

3.3

5.5

REFTS, REFBS reference voltages (MODE = AV

)

PARAMETER

MIN

NOM

MAX

UNIT

REFTS

Reference input voltage (top)

AVDD

REFBS

Reference input voltage (bottom)

AVDD–1

Differential input voltage (REFTS – REFBS)

Switched input capacitance on REFTS or REFBS

0.6

sampling rate and resolution

PARAMETER

MIN

NOM

MAX

UNIT

Sample frequency

MHz

Resolution

Bits

Summary of Contents for THS1031

Page 1: ...ge condition in THS1031 s input signal The format of digital output can be coded in either unsigned binary or 2s complement The speed resolution and single supply operation of the THS1031 are suited to applications in set top box STB video multimedia imaging high speed acquisition and communications The built in clamp function allows dc restoration of video signal and is suitable for video applica...

Page 2: ... OFFICE BOX 655303 DALLAS TEXAS 75265 functional block diagram DAC 10 Bit Clamp 10 Control Register ADC Core Output Buffer 10 PGA 3 Sample and Hold DAC Internal Reference Buffer A B Clamp Amplifier VBG GND Timing Circuit Power Down WR I O 0 9 OVR OE CLK VREF REFSENSE CLAMPIN CLAMP AIN REFTS REFBS MODE REFTF REFBF ORG ...

Page 3: ...al ground DVDD 2 I Digital driver supply I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 I O8 I O9 3 4 5 6 7 8 9 10 11 12 I O Digital I O bit 0 LSB Digital I O bit 1 Digital I O bit 2 Digital I O bit 3 Digital I O bit 4 Digital I O bit 5 Digital I O bit 6 Digital I O bit 7 Digital I O bit 8 Digital I O bit 9 MSB MODE 23 I Mode input OE 16 I High to 3 state the data bus low to enable the data bus OVR 13 O ...

Page 4: ...cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability recommended operating conditions digital inputs MIN NOM MAX UNIT High level input volta...

Page 5: ...ER MIN TYP MAX UNIT Internal 1 V reference voltage REFSENSE VREF 0 95 1 1 05 V Internal 2 V reference voltage REFSENSE AVSS 1 90 2 2 10 V External reference voltage REFSENSE AVDD 1 2 V Reference input resistance REFSENSE AVDD MODE AVDD 2 18 kΩ REFTF REFBF reference voltages PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential input voltage REFTF REFBF 1 2 V Input common mode voltage REFTF REFBF...

Page 6: ... codes 3 Offset error is defined as the difference in analog input voltage between the ideal voltage and the actual voltage that will switch the ADC output from code 0 to code 1 The ideal voltage level is determined by adding the voltage corresponding to 1 2 LSB to the bottom reference level The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the...

Page 7: ...ge range 0 1 AVDD 0 1 V Clamping analog output voltage error 40 40 mV clock PARAMETER MIN TYP MAX UNIT tc Clock cycle 33 ns tw CKH Pulse duration clock high 15 16 5 ns tw CKL Pulse duration clock high 15 16 5 ns td o Clock to data valid delay time 25 ns Pipeline latency 3 Cycles td AP Aperture delay time 4 ns Aperture uncertainty jitter 2 ps timing PARAMETER MIN TYP MAX UNIT td DZ Output disable t...

Page 8: ... Output Output Hi Z Hi Z tw WP td OEW td WOE td DEN tsu th td DZ NOTE A All timing measurements are based on 50 of edge transition Figure 1 Write Timing Diagram See Note A NOTE A All timing measurements are based on 50 of edge transition Analog Input Input Clock Digital Output Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 tc t CKH tw CKL td o Pipeline Latency Sample 1 Sample 2 Figure 2 Digital Outp...

Page 9: ...CAL CHARACTERISTICS 82 84 86 88 90 92 94 96 5 10 15 20 25 30 POWER DISSIPATION vs SAMPLING FREQUENCY fs Sampling Frequency MHz AVDD DVDD 3 V fi 3 5 MHz TA 25 C Power Dissipation mW Figure 3 7 7 5 8 0 8 5 9 0 9 5 10 0 40 15 10 35 60 85 EFFECTIVE NUMBER OF BITS vs TEMPERATURE TA Temperature C AVDD DVDD 3 V fi 3 5 MHz fs 30 MSPS Effective Number of Bits Figure 4 ...

Page 10: ...ICS 7 7 5 8 0 8 5 9 0 9 5 10 0 5 10 15 20 25 30 EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits fs Sampling Frequency MSPS AVDD DVDD 3 V fi 3 5 MHz TA 25 C Figure 5 7 7 5 8 0 8 5 9 0 9 5 10 0 5 10 15 20 25 30 EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits fs Sampling Frequency MSPS AVDD 5 V DVDD 3 V fi 3 5 MHz TA 25 C Figure 6 ...

Page 11: ... 50 8 00 8 50 9 00 9 50 10 00 5 10 15 20 25 30 EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY Effective Number of Bits fs Sampling Frequency MSPS AVDD DVDD 5 V fi 3 5 MHz TA 25 C Figure 7 1 0 8 0 6 0 4 0 2 0 0 0 2 0 4 0 6 0 8 1 0 0 128 256 384 512 640 768 896 1024 DIFFERENTIAL NONLINEARITY vs INPUT CODE Input Code DNL Differential Nonlinearity LSB AVDD 3 V DVDD 3 V fs 30 MSPS Figure 8 ...

Page 12: ...2 0 1 5 1 0 0 5 0 0 0 5 1 0 1 5 2 0 0 128 256 384 512 640 768 896 1024 INTEGRAL NONLINEARITY vs INPUT CODE Input Code INL Integral Nonlinearity LSB AVDD 3 V DVDD 3 V fs 30 MSPS Figure 9 140 120 100 80 60 40 20 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FFT vs FREQUENCY f Frequency MHz AVDD 3 V DVDD 3 V fi 3 5 MHz 1 dBFS FFT dB 0 1 5 3 4 5 6 7 5 9 10 5 12 13 5 15 Figure 10 ...

Page 13: ...10 bit clamp DAC or by the analog level applied to the CLAMPIN input The ADC core drives out through output buffers to the I O pins I O0 to I O9 The output buffers can be disabled by the OE pin Control input data on I O0 to I O9 can then be written by pulses on WR to the control registers These registers control clamp operation output format unsigned binary or twos complement the PGA gain setting ...

Page 14: ...s amplified by the PGA and fed into the ADC as a differential voltage VQ VQ VQ VQ Gain VP Gain AIN VM The default PGA gain at power up is 1 but can be programmed from 0 5 to 4 0 via the control register analog to digital converter In all operating configurations VQ is digitized against ADC reference voltages REFTF and REFBF full scale values of VQ being given by VQFS REFTF REFBF 2 VQFS REFTF REFBF...

Page 15: ...uffer from the voltage applied to the VREF pin This mode is suitable for handling differentially presented inputs which are applied to the AIN and REFTS REFBS pins A special case of differential mode is center span mode in which user applies a single ended signal to AIN and applies the mid scale input voltage VM to the REFTS and REFBS pins Connecting the MODE pin to AVDD gives top bottom mode In t...

Page 16: ...tively These nodes are connected by the user to external sources to provide the ADC reference voltages The internal connections are designed for use in kelvin connection mode Figure 14 When using external reference mode as shown in Figure 13 REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally The mean of REFTF and REFBF must be equal to AVDD 2 see Figure 13 AIN REFTS REFBS...

Page 17: ... 2 AVDD VREF 2 AIN Figure 15 ADC Reference Generation MODE AVDD 2 When MODE AVDD 2 the internal reference buffer is enabled its outputs internally switched to REFTF and REFBF and inputs internally switched to VREF and AGND as shown in Figure 15 The REFTF and REFBF voltages are centered on AVDD 2 by the internal reference buffer and the voltage difference between REFTF and REFBF equals the voltage ...

Page 18: ...CIPLES OF OPERATION differential mode mode AVDD 2 continued AIN REFTS REFBS REFTF REFBF REFSENSE MODE FS FS 0 1 µF 10 µF 0 1 µF 0 1 µF VREF FS FS AIN AIN AVDD 2 Figure 16 Differential Input Mode 1 V Reference Span AIN REFTS REFBS REFTF REFBF REFSENSE MODE FS FS 0 1 µF 10 µF 0 1 µF 0 1 µF VM _ VM DC SOURCE VM AVDD 2 Figure 17 Center Span Mode 2 V Reference Span ...

Page 19: ... REFBS pins and its outputs internally switched to pins REFTF and REFBF The internal connections REFTS to REFTF and REFBS to REFBF are broken To match the signal span to the full ADC input span the voltage difference between REFTS and REFBS should be REFTS REFBS FS FS Gain with the average of the REFTS and REFBS voltages being the AIN midscale voltage VM Typically REFSENSE is tied to AVDD to disab...

Page 20: ...s output to the VREF pin as shown in Table 2 Table 2 Effect of REFSENSE Connection on VREF Value REFSENSE CONNECTION ORG OUTPUT TO VREF REFER TO VREF pin 1 V Figure 20 AGND 2 V Figure 21 External divider junction 1 RA RB Figure 22 AVDD Open circuit Figure 23 REFSENSE AVDD powers the ORG down saving power when the ORG function is not required If MODE AVDD 2 the voltage on VREF determines the ADC re...

Page 21: ...XAS 75265 PRINCIPLES OF OPERATION onboard reference generator configuration continued _ VBG Internal Reference Buffer Mode REFSENSE 0 1 µF 1 µF Tantalum AGND VREF 2 V 10 kΩ 10 kΩ _ AVDD 2 Figure 21 2 V VREF Using ORG _ VBG Internal Reference Buffer Mode REFSENSE 0 1 µF 1 µF Tantalum AGND VREF 1 Ra Rb Ra Rb _ AVDD 2 Figure 22 External Divider Mode ...

Page 22: ...mples of operating configurations Figure 24 shows the operating configuration in top bottom mode for a 2 V span single ended input using VREF to drive REFTS and with PGA gain 1 Connecting the MODE pin to AVDD puts the THS1031 in top bottom mode Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V REFTS and REFBS are user connected to VREF and AGND respectively to match the AIN pin inp...

Page 23: ...AIN REFTS REFBS REFTF REFBF REFSENSE MODE 1 4 V 0 6 V 0 1 µF 10 µF 0 1 µF 0 1 µF VREF 1 6 V RA RB 1 V 1 4 V 0 6 V 1 V AIN AIN AVDD 2 Figure 25 Differential Operation Figure 26 shows a center span configuration for an input waveform swinging between 0 2 and 1 9 V Pins REFTS and REFBS are connected to a voltage source of 1 05 V equal to the mid scale of the input waveform With the PGA gain set to it...

Page 24: ...1 µF 1 5 V DC SOURCE 2 5 V DC SOURCE 0 5 V REFSENSE Figure 27 Top Bottom Mode PGA Gain 2 5 clamp operation 10 Bit DAC _ CLAMPIN CLAMP AIN RIN CIN V Clamp Control Register Bit CLINT S H VIN SW1 Figure 28 Schematic of Clamp Circuitry The THS1031 provides a clamp function for restoring a dc reference level to the signal at AIN which has been lost through ac coupling from the signal source to this pin...

Page 25: ...s range VREFBF to VREFTF Specifically VDAC VREFBF VREFTF VREFBF 0 006 0 988 DAC code ń1024 DAC codes can range from 0 to 1023 Figure 30 graphically shows the clamp DAC output voltage versus the DAC code VDAC 0 1023 VREFBF 0 006 VREFTF VREFBF VREFBF 0 987 VREFTF VREFBF DAC Code VREFTF VREFBF Figure 30 Clamp DAC Output Voltage Versus DAC Register Code Value If the desired dc level at AIN does not li...

Page 26: ...at pin OVR OVR is also disabled when OE is held high The default ADC output data format is unsigned binary output codes 0 to 1023 The output format can be switched to 2s complement output codes 512 to 511 by setting control register bit 5 TWOC to 1 writing to the internal registers through the digital I O bus Pulling pin OE high disables the I O and OVR pin output drivers placing the driver output...

Page 27: ... 4 DAC 3 DAC 2 DAC 1 DAC 0 01 Clamp Reg 2 00 DAC 9 DAC 8 10 Control Reg 01 CLDIS TWOC CLINT PDWN PGA 2 PGA 1 PGA 0 11 Reserved Table 4 Register Contents REGISTER BIT NO BIT NAME S DEFAULT DESCRIPTION 2 0 PGA 2 0 0 PGA gain 000 0 5 001 1 0 default value 010 1 5 011 2 0 100 2 5 101 3 0 110 3 5 111 4 0 Control Register I O 9 8 10 3 PDWN 0 Power down 0 THS1031 powered up 1 THS1031 powered down I O 9 8...

Page 28: ...n AIN input current and input load modeling When CLK goes low the source driving AIN must charge the total switched capacitance CS CSAMPLE CP2 The total charge transferred depends on the voltage at AIN and is given by Q CHARGING AIN V LAST C S For a fixed voltage at AIN so that AIN and VLAST do not change between samples the maximum amount of charge transfer occurs at AIN FS charging current flows...

Page 29: ...es as shown in Figure 34 then additional filtering should be used to ensure that noise from the supplies does not reach AIN Working with the input current pulse equations given in the previous section is awkward when designing ac coupling input networks For such design it is much simpler to model the AIN input as an equivalent resistance RAIN from the AIN pin to a voltage source VM where VM REFTS ...

Page 30: ...t charging pulse IIN Qin tclk Qin fclk Vin VLAST CS fclk The ac input resistance RAIN is then RAIN dIin dVin 1 dVin dIin 1 CS x fclk driving the VREF pin differential mode Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin MODE AVDD 2 and REFSENSE AVDD AVDD AGND AVDD VREF 4 VREF RIN 14 kΩ REFSENSE AVDD Mode _ 4 4 AVDD 2 Figure 35 Equivalent ...

Page 31: ...l Reference Buffer Equations for the currents flowing into REFTS and REFBS are I IN TS 3 REFTS AV DD REFBS 4 R IN I IN BS 3 REFBS AV DD REFTS 4 R IN These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold Tolerance on these currents are 50 driving REFTS and REFBS C1 7 pF AVDD AGND CLK CLK C2 0 6 pF 0 6 pF CSAMPLE VLAST REFTS ...

Page 32: ... Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit 10 Bit DAC _ CLAMPIN CLAMP AIN RIN CIN VCLAMP Control Register S H VIN SW1 Figure 39 Schematic of Clamp Circuitry After powerup the clamp circuit requires SW1 to be closed to charge the coupling capacitor CIN to the voltage required to set the dc clamp level at AIN The charging time requir...

Page 33: ...AIN to drift toward VM the average of REFTS and REFBS during the time between clamp pulses This effect is called clamp droop and can be seen as a slow change in the ADC output code when the input signal is a constant dc level Through careful clamp circuit design this droop can be kept below 1 LSB giving no change in the ADC output between clamp pulses The clamp voltage droop is a function of the i...

Page 34: ... frequencies steady state clamp voltage error Under steady state conditions the change in the clamp voltage caused during clamping must equal the change caused by clamp droop otherwise the effect causing the largest voltage change would pull the clamp voltage away until these charging and droop effects equalize Figure 40 shows the approximate voltage waveform at AIN resulting from clamp droop duri...

Page 35: ...mized by buffering the THS1031 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible and by using the shortest possible tracks between the THS1031 and this buffer Noise levels at the output buffers and hence coupling to the analog circuits within THS1031 becomes worse as the THS1031 digital supply voltage is increased Where possible consider ...

Page 36: ...004 0 10 A 8 16 0 020 0 51 0 014 0 35 0 293 7 45 0 299 7 59 9 0 010 0 25 0 050 1 27 0 016 0 40 15 24 15 49 PINS 0 010 0 25 NOM A MAX DIM A MIN Gage Plane 20 0 500 12 70 12 95 0 510 10 16 10 41 0 400 0 410 16 0 600 24 0 610 17 78 28 0 700 18 03 0 710 0 004 0 10 M 0 010 0 25 0 050 1 27 0 8 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice C Bo...

Page 37: ... 10 0 25 0 50 0 75 0 15 NOM Gage Plane 28 9 80 9 60 24 7 90 7 70 20 16 6 60 6 40 4040064 F 01 97 0 30 6 60 6 20 8 0 19 4 30 4 50 7 0 15 14 A 1 1 20 MAX 14 5 10 4 90 8 3 10 2 90 A MAX A MIN DIM PINS 0 05 4 90 5 10 Seating Plane 0 8 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protrusion not to exce...

Page 38: ...ined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component ...

Page 39: ...ce Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant THS1031CPWR TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 11 Mar 2008 Pack Materials Page 1 ...

Page 40: ...sions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm THS1031CPWR TSSOP PW 28 2000 346 0 346 0 33 0 PACKAGE MATERIALS INFORMATION www ti com 11 Mar 2008 Pack Materials Page 2 ...

Page 41: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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