THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
32
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
driving REFTF and REFBF (full external reference mode)
AVDD
AGND
AVDD
AGND
680
Ω
To REFBS
(For Kelvin Connection)
To REFTS
(For Kelvin Connection)
REFTF
REFBF
Figure 38. Equivalent Circuit of REFTF and REFBF Inputs
Note the need for off-chip decoupling.
clamp operation
The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by
programming the on-chip clamp DAC.
clamp acquisition time
Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.
10-Bit
DAC
_
+
CLAMPIN
CLAMP
AIN
RIN
CIN
VCLAMP
Control Register
S/H
VIN
SW1
Figure 39. Schematic of Clamp Circuitry
After powerup, the clamp circuit requires SW1 to be closed to charge the coupling capacitor, C
IN
, to the voltage
required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called
the clamp acquisition time, t
ACQ
:
t
ACQ
+
C
IN
R
IN
In
ǒ
Vc
Ve
Ǔ
Vc is the difference between the dc bias voltage level of the input signal, V
IN
, and the target clamp output voltage,
V
(clamp)
. Ve is the difference between the ideal Vc and the actual Vc obtained during the acquisition time. The
maximum tolerable error depends on the application requirements.
(19)
