THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
31
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
driving the internal reference buffer (top/bottom mode)
Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal
reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.
AVDD
AGND
AVDD + REFTS + REFBS
REFTS
REFBS
RIN
14 k
Ω
Mode =
_
+
4
AVDD
2
Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer
Equations for the currents flowing into REFTS and REFBS are:
I
IN
TS
+
( 3
REFTS
*
AV
DD
*
REFBS )
(4
R
IN
)
I
IN
BS
+
(3
REFBS
*
AV
DD
*
REFTS )
(4
R
IN
)
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving
the sample and hold. Tolerance on these currents are
±
50%.
driving REFTS and REFBS
C1
7 pF
AVDD
AGND
CLK
CLK
C2
0.6 pF
0.6 pF
CSAMPLE
VLAST
REFTS
REFBS
Mode = AVDD
Internal
Reference
Buffer
_
+
Figure 37. Equivalent Circuit of REFTS and REFBS Inputs
This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also
driving a switched capacitor load like AIN, but with the sampling capacitor and C
P2
on each pin now being 0.6 pF
and about 0.6 pF respectively.
(18)
