THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
30
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
details
The above value for R
AIN
is derived by noting that the average AIN voltage must equal the bias voltage supplied
by the ac coupling network. The average value of V
LAST
in equation 13 is thus a constant voltage
V
LAST
= V(AIN bias) – VM
For an input voltage V
in
at the AIN pin,
Qin = (V
IN
– V
LAST
)
×
C
S
Provided that f (–3 dB) is much lower than f
clk
, a constant current flowing over the clock period can approximate
the input charging pulse
I
IN
= Qin/t
clk
= Qin
×
f
clk
= (Vin – V
LAST
)
×
C
S
×
f
clk
The ac input resistance R
AIN
is then
R
AIN
= dIin/dVin
= 1 / (dVin / dIin)
= 1 / (C
S
x f
clk
)
driving the VREF pin (differential mode)
Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin
(MODE = AV
DD
/2 and REFSENSE = AV
DD
).
AVDD
AGND
AVDD + VREF/4
VREF
RIN
14 k
Ω
REFSENSE = AVDD,
Mode =
_
+
4
4
AVDD
2
Figure 35. Equivalent Circuit of VREF
The current flowing into I
IN
is given by
I
IN
+
(3
VREF
*
AV
DD
)
(4
R
IN
)
Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations
and allowing for operating temperature variations.
The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground
and capable of driving I
IN
.
(13)
(14)
(15)
(16)
(17)
