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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352

SPRS717H – OCTOBER 2011 – REVISED MAY 2015

7.10.2 LCD Raster Mode

Table 7-76. Switching Characteristics for LCD Raster Mode

(see

through

OPP50

OPP100

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

t

c(LCD_PCLK)

Cycle time, pixel clock

15.8

7.9

ns

2

t

w(LCD_PCLKH)

Pulse duration, pixel clock high

0.45t

c

0.55t

c

0.45t

c

0.55t

c

ns

3

t

w(LCD_PCLKL)

Pulse duration, pixel clock low

0.45t

c

0.55t

c

0.45t

c

0.55t

c

ns

Delay time, LCD_PCLK to LCD_DATA[23:0] valid

4

t

d(LCD_PCLK-LCD_DATAV)

3.0

1.9

ns

(write)

Delay time, LCD_PCLK to LCD_DATA[23:0] invalid

5

t

d(LCD_PCLK-LCD_DATAI)

–3.0

–1.7

ns

(write)

6

t

d(LCD_PCLK-LCD_AC_BIAS_EN)

Delay time, LCD_PCLK to LCD_AC_BIAS_EN

–3.0

3.0

–1.7

1.9

ns

7

t

t(LCD_AC_BIAS_EN)

Transition time, LCD_AC_BIAS_EN

0.5

2.4

0.5

2.4

ns

8

t

d(LCD_PCLK-LCD_VSYNC)

Delay time, LCD_PCLK to LCD_VSYNC

–3.0

3.0

–1.7

1.9

ns

9

t

t(LCD_VSYNC)

Transition time, LCD_VSYNC

0.5

2.4

0.5

2.4

ns

10

t

d(LCD_PCLK-LCD_HSYNC)

Delay time, LCD_PCLK to LCD_HSYNC

–3.0

3.0

–1.7

1.9

ns

11

t

t(LCD_HSYNC)

Transition time, LCD_HSYNC

0.5

2.4

0.5

2.4

ns

12

t

t(LCD_PCLK)

Transition time, LCD_PCLK

0.5

2.4

0.5

2.4

ns

13

t

t(LCD_DATA)

Transition time, LCD_DATA

0.5

2.4

0.5

2.4

ns

Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:

•

Vertical front porch (VFP)

•

Vertical sync pulse width (VSW)

•

Vertical back porch (VBP)

•

Lines per panel (L LPP)

Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:

•

Horizontal front porch (HFP)

•

Horizontal sync pulse width (HSW)

•

Horizontal back porch (HBP)

•

Pixels per panel ( PPLLSB)

LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:

•

AC bias frequency (ACB)

The display format produced in raster mode is shown in

. An entire frame is delivered one line

at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of IO signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of IO signal LCD_HSYNC.

204

Peripheral Information and Timings

Copyright © 2011–2015, Texas Instruments Incorporated

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Summary of Contents for Sitara AM335x

Page 1: ...esources Inside DDR2 266 MHz Clock 532 MHz Data Rate the PRU ICSS DDR3 400 MHz Clock 800 MHz Data Rate Peripherals Inside the PRU ICSS DDR3L 400 MHz Clock 800 MHz Data One UART Port With Flow Control Pins Rate Supports up to 12 Mbps 16 Bit Data Bus One Enhanced Capture eCAP Module 1GB of Total Addressable Space Two MII Ethernet Ports that Support Industrial Ethernet such as EtherCAT Supports One x...

Page 2: ...or Wakeup or Other Functional Pins Cortex A8 for Event Notification GPIO Pins Can be Used as Interrupt Inputs Programmable Alarm Can be Used With up to Two Interrupt Inputs per Bank External Output PMIC_POWER_EN to Enable Up to Three External DMA Event Inputs that can the Power Management IC to Restore Non RTC Also be Used as Interrupt Inputs Power Domains Eight 32 Bit General Purpose Timers Perip...

Page 3: ...al Storage External Frame Buffer Space and the EMIF GPMC Slave Peripherals Internal DMA Engine to Drive Streaming Inter Processor Communication IPC Data to the Panel Integrates Hardware Based Mailbox for IPC and 12 Bit Successive Approximation Register Spinlock for Process Synchronization Between SAR ADC Cortex A8 PRCM and PRU ICSS 200K Samples per Second Mailbox Registers that Generate Interrupts...

Page 4: ...he PRU ICSS enables additional peripheral interfaces and real time protocols such as EtherCAT PROFINET EtherNet IP PROFIBUS Ethernet Powerlink Sercos and others Additionally the programmable nature of the PRU ICSS along with its access to pins events and all system on chip SoC resources provides flexibility in implementing fast real time responses specialized data handling operations custom periph...

Page 5: ...channel 12 bit SAR JTAG Crystal Oscillator x2 MMC SD and SDIO x3 GPIO EMAC 2 port 10M 100M 1G IEEE 1588v2 and switch MII RMII RGMII mDDR LPDDR DDR2 DDR3 DDR3L 16 bit 200 266 400 400 MHz NAND and NOR 16 bit ECC Memory interface AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 1 4 Functional Block Diagram Figure 1 1 shows the AM335x microprocessor functiona...

Page 6: ...e Unit Subsystem and 5 3 Power On Hours POH 82 Industrial Communication Subsystem PRU ICSS 224 5 4 Operating Performance Points OPPs 82 7 15 Universal Asynchronous Receiver Transmitter UART 233 5 5 Recommended Operating Conditions 85 8 Device and Documentation Support 236 5 6 Power Consumption Summary 87 8 1 Device Support 236 5 7 DC Electrical Characteristics 89 8 2 Documentation Support 238 5 8 ...

Page 7: ...meter F7 F15 and F17 OPP50 MAX value and added Footnote to F7 F15 and F17 added additional Parameters F7 F15 and F17 and corresponding Footnotes in Table 7 22 128 Deleted FAST MODE MIN values for Parameters 9 12 and Footnote 4 in Table 7 69 These values were incorrectly added in Revision G 191 Deleted FAST MODE MIN values for Parameters 23 26 and Footnote 1 in Table 7 70 These values were incorrec...

Page 8: ...urpose memory 1 16 bit GPMC 1 16 bit GPMC 1 16 bit GPMC 1 16 bit GPMC 1 16 bit GPMC 1 16 bit GPMC NAND flash NAND flash NAND flash NAND flash NAND flash NAND flash NOR flash NOR flash NOR flash NOR flash NOR flash NOR flash SRAM SRAM SRAM SRAM SRAM SRAM DRAM 3 1 16 bit LPDDR 1 16 bit LPDDR 1 16 bit LPDDR 1 16 bit LPDDR 1 16 bit LPDDR 1 16 bit LPDDR 400 DDR2 532 400 DDR2 532 400 DDR2 532 400 DDR2 5...

Page 9: ...C 4 40 to 105 C 40 to 105 C 40 to 105 C 40 to 105 C 40 to 105 C 40 to 105 C 40 to 90 C 40 to 90 C 40 to 90 C 40 to 90 C 40 to 90 C 40 to 90 C 0 to 90 C 0 to 90 C 0 to 90 C 0 to 90 C 1 Frequencies listed correspond to silicon revision 2 1 Earlier silicon revisions support 275 MHz 500 MHz 600 MHz and 720 MHz 2 MPIS listed correspond to silicon revision 2 1 Earlier silicon revisions support 560 1000 ...

Page 10: ...ghout the document An attempt is made to use ball only when referring to the physical package 4 1 1 ZCE Package Pin Maps Top View The pin maps below show the pin assignments on the ZCE package in three sections left middle and right 10 Terminal Configuration and Functions Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM33...

Page 11: ...2 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS 11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE 10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX 9 VREFP VREFN XXXX XXXX VSS VDD_CORE 8 AIN2 AIN0 AIN4 VSSA_ADC VSS VSS 7 RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS 6 RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS 5 RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX 4 DDR_WEn DDR_BA2 ...

Page 12: ...XXX VDD_CORE VDD_CORE 12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 11 VDD_CORE VSS VSS VSS VSS VSS 10 XXXX VSS XXXX XXXX XXXX VSS 9 VDD_CORE VSS VSS VSS VSS VSS 8 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 7 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE 6 XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR 5 VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR 4 DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11 3 DDR_CKE DDR...

Page 13: ...2 XTALOUT 11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN 10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0 9 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn 8 VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0 7 XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN 6 XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14 5 VDDS_DDR XXXX VPP XXXX LCD_DA...

Page 14: ...age Pin Maps Top View The pin maps below show the pin assignments on the ZCZ package in three sections left middle and right 14 Terminal Configuration and Functions Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 15: ...CASP0_AXR0 VDDSHV6 VDD_MPU 11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU 10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU 9 VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS 8 AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS 7 AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE 6 RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE 5 VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_D...

Page 16: ...S VSS VDD_CORE 12 VSS VSS VDD_CORE VDD_CORE VSS VSS 11 VSS VDD_CORE VSS VSS VSS VDD_CORE 10 VDD_CORE VSS VSS VSS VSS VSS 9 VSS VSS VSS VSS VDD_CORE VSS 8 VSS VSS VSS VDD_CORE VDD_CORE VSS 7 VDD_CORE VSS VSS VSS VDD_CORE VSS 6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS 5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP 4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1 3 DDR_CKE DDR_A13 DDR_VTP DDR_D11...

Page 17: ...DS_OSC GPMC_AD10 XTALOUT VSS_OSC 10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN 9 VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2 8 VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5 7 VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1 6 VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0 5 VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK 4 DDR_D5 DDR_D7 LCD_...

Page 18: ...modes are effectively used for alternate functions while some modes are not used and do not correspond to a functional configuration 5 TYPE Signal direction I Input O Output I O Input and Output D Open drain DS Differential A Analog PWR Power GND Ground Note In the safe_mode the buffer is configured in high impedance 6 BALL RESET STATE State of the terminal while the active low PWRONRSTn terminal ...

Page 19: ...p or pulldown resistor Pullup and pulldown resistors can be enabled or disabled via software 13 IO CELL IO cell information Note Configuring two terminals to the same input signal is not supported as it can yield unexpected results This can be easily prevented with the proper software configuration Copyright 2011 2015 Texas Instruments Incorporated Terminal Configuration and Functions 19 Submit Do...

Page 20: ...SRAM_CORE NA A D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS...

Page 21: ...KE ddr_cke 0 O L 0 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL C1 D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL H2 H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL N4 M3 DDR_D0 ddr_d0 0 I O L Z 0 VDDS_DDR Yes 8 PU PD LVCMOS SSTL VDDS_DDR HSTL P4 M4 DDR_D1 ddr_d1 0 I O L Z 0 VDDS_DDR Yes 8 PU PD LVCMOS SSTL VDDS_DDR HSTL P2 N1 DDR_D2 ddr_...

Page 22: ...R HSTL L1 L1 DDR_DQS1 ddr_dqs1 0 I O L Z 0 VDDS_DDR Yes 8 PU PD LVCMOS SSTL VDDS_DDR HSTL R2 P2 DDR_DQSn0 ddr_dqsn0 0 I O H Z 0 VDDS_DDR Yes 8 PU PD LVCMOS SSTL VDDS_DDR HSTL L2 L2 DDR_DQSn1 ddr_dqsn1 0 I O H Z 0 VDDS_DDR Yes 8 PU PD LVCMOS SSTL VDDS_DDR HSTL G1 G1 DDR_ODT ddr_odt 0 O L 0 0 VDDS_DDR NA 8 PU PD LVCMOS SSTL VDDS_DDR HSTL F2 G4 DDR_RASn ddr_rasn 0 O H 1 0 VDDS_DDR NA 8 PU PD LVCMOS S...

Page 23: ...s 6 PU PD LVCMOS gmii2_txen 1 O rgmii2_tctl 2 O rmii2_txen 3 O gpmc_a16 4 O pr1_mii_mt1_clk 5 I ehrpwm1_tripzone_input 6 I gpio1_16 7 I O NA V14 GPMC_A1 gpmc_a1 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxdv 1 I rgmii2_rctl 2 I mmc2_dat0 3 I O gpmc_a17 4 O pr1_mii1_txd3 5 O ehrpwm0_synco 6 O gpio1_17 7 I O NA U14 GPMC_A2 gpmc_a2 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txd3 1 O rgmii2_td3...

Page 24: ... gpio1_20 7 I O NA V15 GPMC_A5 gpmc_a5 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txd0 1 O rgmii2_td0 2 O rmii2_txd0 3 O gpmc_a21 4 O pr1_mii1_rxd3 5 I eQEP1B_in 6 I gpio1_21 7 I O NA U15 GPMC_A6 gpmc_a6 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_txclk 1 I rgmii2_tclk 2 O mmc2_dat4 3 I O gpmc_a22 4 O pr1_mii1_rxd2 5 I eQEP1_index 6 I O gpio1_22 7 I O NA T15 GPMC_A7 gpmc_a7 0 O L L 7 NA VDDSH...

Page 25: ...2 I mmc2_dat7 rmii2_crs_dv 3 I O gpmc_a25 4 O pr1_mii_mr1_clk 5 I mcasp0_fsx 6 I O gpio1_25 7 I O NA T16 GPMC_A10 gpmc_a10 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxd1 1 I rgmii2_rd1 2 I rmii2_rxd1 3 I gpmc_a26 4 O pr1_mii1_rxdv 5 I mcasp0_axr0 6 I O gpio1_26 7 I O NA V17 GPMC_A11 gpmc_a11 0 O L L 7 NA VDDSHV3 Yes 6 PU PD LVCMOS gmii2_rxd0 1 I rgmii2_rd0 2 I rmii2_rxd0 3 I gpmc_a27 4 O pr1_m...

Page 26: ...dat4 1 I O gpio1_4 7 I O W14 V8 GPMC_AD5 gpmc_ad5 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 mmc1_dat5 1 I O gpio1_5 7 I O U14 R9 GPMC_AD6 gpmc_ad6 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 mmc1_dat6 1 I O gpio1_6 7 I O W15 T9 GPMC_AD7 gpmc_ad7 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 mmc1_dat7 1 I O gpio1_7 7 I O V15 U10 GPMC_AD8 gpmc_ad8 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDS...

Page 27: ...dat3 2 I O mmc2_dat7 3 I O ehrpwm0_synco 4 O pr1_mii0_txd3 5 O gpio0_27 7 I O U13 T12 GPMC_AD12 gpmc_ad12 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV2 lcd_data19 1 O mmc1_dat4 2 I O mmc2_dat0 3 I O eQEP2A_in 4 I pr1_mii0_txd2 5 O pr1_pru0_pru_r30_14 6 O gpio1_12 7 I O T13 R12 GPMC_AD13 gpmc_ad13 0 I O L L 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV2 lcd_data18 1 O mmc1_dat5 2 I O mmc2_dat1 3 I O eQEP2B_...

Page 28: ...O H H 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 timer4 2 I O gpio2_2 7 I O V8 T6 GPMC_BEn0_CLE gpmc_be0n_cle 0 O H H 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 timer5 2 I O gpio2_5 7 I O V18 U18 GPMC_BEn1 gpmc_be1n 0 O H H 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV3 gmii2_col 1 I gpmc_csn6 2 O mmc2_dat3 3 I O gpmc_dir 4 O pr1_mii1_rxlink 5 I mcasp0_aclkr 6 I O gpio1_28 7 I O V16 V12 GPMC_CLK gpmc_clk 0 I O L L 7 VD...

Page 29: ...c1_cmd 2 I O pr1_edio_data_in7 3 I pr1_edio_data_out7 4 O pr1_pru1_pru_r30_13 5 O pr1_pru1_pru_r31_13 6 I gpio1_31 7 I O U17 T13 GPMC_CSn3 6 gpmc_csn3 0 O H H 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV2 gpmc_a3 1 O rmii2_crs_dv 2 I mmc2_cmd 3 I O pr1_mii0_crs 4 I pr1_mdio_data 5 I O EMU4 6 I O gpio2_0 7 I O W9 T7 GPMC_OEn_REn gpmc_oen_ren 0 O H H 7 VDDSHV1 Yes 6 PU PD LVCMOS VDDSHV1 timer7 2 I O gpio2_3 ...

Page 30: ...LVCMOS VDDSHV6 timer4 1 I O uart2_ctsn 2 I eCAP2_in_PWM2_out 3 I O gpio3_5 7 I O B19 C16 I2C0_SCL I2C0_SCL 0 I OD Z H 7 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 timer7 1 I O uart2_rtsn 2 O eCAP1_in_PWM1_out 3 I O gpio3_6 7 I O W7 R6 LCD_AC_BIAS_EN lcd_ac_bias_en 0 O Z L 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a11 1 O pr1_mii1_crs 2 I pr1_edio_data_in5 3 I pr1_edio_data_out5 4 O pr1_pru1_pru_r30_11 5 O...

Page 31: ...pr1_mii0_txd3 2 O ehrpwm2_tripzone_input 3 I pr1_pru1_pru_r30_2 5 O pr1_pru1_pru_r31_2 6 I gpio2_8 7 I O V2 R4 LCD_DATA3 5 lcd_data3 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a3 1 O pr1_mii0_txd2 2 O ehrpwm0_synco 3 O pr1_pru1_pru_r30_3 5 O pr1_pru1_pru_r31_3 6 I gpio2_9 7 I O W2 T1 LCD_DATA4 5 lcd_data4 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a4 1 O pr1_mii0_txd1 2 O eQEP2A_...

Page 32: ... U3 T4 LCD_DATA7 5 lcd_data7 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a7 1 O pr1_edio_data_in7 2 I eQEP2_strobe 3 I O pr1_edio_data_out7 4 O pr1_pru1_pru_r30_7 5 O pr1_pru1_pru_r31_7 6 I gpio2_13 7 I O V4 U1 LCD_DATA8 5 lcd_data8 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a12 1 O ehrpwm1_tripzone_input 2 I mcasp0_aclkx 3 I O uart5_txd 4 O pr1_mii0_rxd3 5 I uart2_ctsn 6 I gpio2_...

Page 33: ...LCD_DATA11 5 lcd_data11 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a15 1 O ehrpwm1B 2 O mcasp0_ahclkr 3 I O mcasp0_axr2 4 I O pr1_mii0_rxd0 5 I uart3_rtsn 6 O gpio2_17 7 I O V6 V2 LCD_DATA12 5 lcd_data12 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a16 1 O eQEP1A_in 2 I mcasp0_aclkr 3 I O mcasp0_axr2 4 I O pr1_mii0_rxlink 5 I uart4_ctsn 6 I gpio0_8 7 I O U6 V3 LCD_DATA13 5 lcd_data...

Page 34: ... 5 lcd_data15 0 I O Z Z 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a19 1 O eQEP1_strobe 2 I O mcasp0_ahclkx 3 I O mcasp0_axr3 4 I O pr1_mii0_rxdv 5 I uart5_rtsn 6 O gpio0_11 7 I O T7 R5 LCD_HSYNC 7 lcd_hsync 0 O Z L 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 gpmc_a9 1 O gpmc_a2 2 O pr1_edio_data_in3 3 I pr1_edio_data_out3 4 O pr1_pru1_pru_r30_9 5 O pr1_pru1_pru_r31_9 6 I gpio2_23 7 I O W5 V5 LCD_PCLK lcd...

Page 35: ...NA B13 MCASP0_FSX mcasp0_fsx 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS ehrpwm0B 1 O spi1_d0 3 I O mmc1_sdcd 4 I pr1_pru0_pru_r30_1 5 O pr1_pru0_pru_r31_1 6 I gpio3_15 7 I O NA B12 MCASP0_ACLKR mcasp0_aclkr 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS eQEP0A_in 1 I mcasp0_axr2 2 I O mcasp1_aclkx 3 I O mmc0_sdwp 4 I pr1_pru0_pru_r30_4 5 O pr1_pru0_pru_r31_4 6 I gpio3_18 7 I O NA C12 MCASP0_AHCLKR mcasp...

Page 36: ...rpwm0A 1 O spi1_sclk 3 I O mmc0_sdcd 4 I pr1_pru0_pru_r30_0 5 O pr1_pru0_pru_r31_0 6 I gpio3_14 7 I O NA C13 MCASP0_FSR mcasp0_fsr 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS eQEP0B_in 1 I mcasp0_axr3 2 I O mcasp1_fsx 3 I O EMU2 4 I O pr1_pru0_pru_r30_5 5 O pr1_pru0_pru_r31_5 6 I gpio3_19 7 I O NA D12 MCASP0_AXR0 mcasp0_axr0 0 I O L L 7 NA VDDSHV6 Yes 6 PU PD LVCMOS ehrpwm0_tripzone_input 1 I spi1_d...

Page 37: ...O P17 M17 MDIO mdio_data 0 I O H H 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 timer6 1 I O uart5_rxd 2 I uart3_ctsn 3 I mmc0_sdcd 4 I mmc1_cmd 5 I O mmc2_cmd 6 I O gpio0_0 7 I O L19 J17 MII1_RX_DV gmii1_rxdv 0 I L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 lcd_memory_clk 1 O rgmii1_rctl 2 I uart5_txd 3 O mcasp1_aclkx 4 I O mmc2_dat0 5 I O mcasp0_aclkr 6 I O gpio3_4 7 I O K17 J16 MII1_TX_EN gmii1_txen 0 O L ...

Page 38: ... O M19 L18 MII1_RX_CLK gmii1_rxclk 0 I L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 uart2_txd 1 O rgmii1_rclk 2 I mmc0_dat6 3 I O mmc1_dat1 4 I O uart1_dsrn 5 I mcasp0_fsx 6 I O gpio3_10 7 I O N19 K18 MII1_TX_CLK gmii1_txclk 0 I L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 uart2_rxd 1 I rgmii1_tclk 2 O mmc0_dat7 3 I O mmc1_dat0 4 I O uart1_dcdn 5 I mcasp0_aclkx 6 I O gpio3_9 7 I O J19 H16 MII1_COL gmii1_c...

Page 39: ...18 M16 MII1_RXD0 gmii1_rxd0 0 I L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 rmii1_rxd0 1 I rgmii1_rd0 2 I mcasp1_ahclkx 3 I O mcasp1_ahclkr 4 I O mcasp1_aclkr 5 I O mcasp0_axr3 6 I O gpio2_21 7 I O P19 L15 MII1_RXD1 gmii1_rxd1 0 I L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 rmii1_rxd1 1 I rgmii1_rd1 2 I mcasp1_axr3 3 I O mcasp1_fsr 4 I O eQEP0_strobe 5 I O mmc2_clk 6 I O gpio2_20 7 I O N16 L16 MII1_RXD2...

Page 40: ... 7 I O L18 K17 MII1_TXD0 gmii1_txd0 0 O L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 rmii1_txd0 1 O rgmii1_td0 2 O mcasp1_axr2 3 I O mcasp1_aclkr 4 I O eQEP0B_in 5 I mmc1_clk 6 I O gpio0_28 7 I O M18 K16 MII1_TXD1 gmii1_txd1 0 O L L 7 VDDSHV5 Yes 6 PU PD LVCMOS VDDSHV5 rmii1_txd1 1 O rgmii1_td1 2 O mcasp1_fsr 3 I O mcasp1_axr1 4 I O eQEP0A_in 5 I mmc1_cmd 6 I O gpio0_21 7 I O N18 K15 MII1_TXD2 gmii1_t...

Page 41: ...8 MMC0_CMD mmc0_cmd 0 I O H H 7 VDDSHV4 Yes 6 PU PD LVCMOS VDDSHV4 gpmc_a25 1 O uart3_rtsn 2 O uart2_txd 3 O dcan1_rx 4 I pr1_pru0_pru_r30_13 5 O pr1_pru0_pru_r31_13 6 I gpio2_31 7 I O G19 G17 MMC0_CLK mmc0_clk 0 I O H H 7 VDDSHV4 Yes 6 PU PD LVCMOS VDDSHV4 gpmc_a24 1 O uart3_ctsn 2 I uart2_rxd 3 I dcan1_tx 4 O pr1_pru0_pru_r30_12 5 O pr1_pru0_pru_r31_12 6 I gpio2_30 7 I O G18 G16 MMC0_DAT0 mmc0_d...

Page 42: ... 5 O pr1_pru0_pru_r31_9 6 I gpio2_27 7 I O H19 F17 MMC0_DAT3 mmc0_dat3 0 I O H H 7 VDDSHV4 Yes 6 PU PD LVCMOS VDDSHV4 gpmc_a20 1 O uart4_ctsn 2 I timer5 3 I O uart1_dcdn 4 I pr1_pru0_pru_r30_8 5 O pr1_pru0_pru_r31_8 6 I gpio2_26 7 I O C7 C6 PMIC_POWER_EN PMIC_POWER_EN 0 O H 1 0 VDDS_RTC NA 6 NA LVCMOS VDDS_RTC E15 B15 PWRONRSTn porz 0 I Z Z 0 VDDSHV6 Yes NA NA LVCMOS VDDSHV6 12 B6 A3 RESERVED 3 te...

Page 43: ...VDDSHV6 uart2_rxd 1 I I2C2_SDA 2 I OD ehrpwm0A 3 O pr1_uart0_cts_n 4 I pr1_edio_sof 5 O EMU2 6 I O gpio0_2 7 I O A17 A16 SPI0_CS0 spi0_cs0 0 I O Z H 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 mmc2_sdwp 1 I I2C1_SCL 2 I OD ehrpwm0_synci 3 I pr1_uart0_txd 4 O pr1_edio_data_in1 5 I pr1_edio_data_out1 6 O gpio0_5 7 I O B16 C15 SPI0_CS1 spi0_cs1 0 I O Z H 7 VDDSHV6 Yes 6 PU PD LVCMOS VDDSHV6 uart3_rxd 1 I eC...

Page 44: ...VDDSHV6 B13 B11 TDI TDI 0 I H H 0 VDDSHV6 Yes NA PU PD LVCMOS VDDSHV6 A14 A11 TDO TDO 0 O H H 0 VDDSHV6 NA 4 PU PD LVCMOS VDDSHV6 C14 C11 TMS TMS 0 I H H 0 VDDSHV6 Yes NA PU PD LVCMOS VDDSHV6 A13 B10 TRSTn nTRST 0 I L L 0 VDDSHV6 Yes NA PU PD LVCMOS VDDSHV6 F17 E16 UART0_TXD uart0_txd 0 O Z H 7 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 spi1_cs1 1 I O dcan0_rx 2 I I2C2_SCL 3 I OD eCAP1_in_PWM1_out 4 I O p...

Page 45: ...S VDDSHV6 uart4_txd 1 O dcan1_rx 2 I I2C1_SCL 3 I OD spi1_d1 4 I O spi1_cs0 5 I O pr1_edc_sync1_out 6 O gpio1_9 7 I O C19 D15 UART1_TXD uart1_txd 0 O Z H 7 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 mmc2_sdwp 1 I dcan1_rx 2 I I2C1_SCL 3 I OD pr1_uart0_txd 5 O pr1_pru0_pru_r31_16 6 I gpio0_15 7 I O D18 D16 UART1_RXD uart1_rxd 0 I Z H 7 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 mmc1_sdwp 1 I dcan1_tx 2 O I2C1_SDA ...

Page 46: ...VBUS 0 O L 0 PD 0 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 gpio0_18 7 I O V19 P16 USB0_ID USB0_ID 0 A Z Z 0 VDDA _USB0 NA NA NA Analog VDDA _USB0 26 U19 N17 USB0_DP USB0_DP 0 A Z Z 0 13 VDDA _USB0 Yes 8 16 NA Analog VDDA _USB0 16 26 NA P18 USB1_CE USB1_CE 0 A Z Z 0 NA NA NA NA Analog VDDA _USB1 27 NA P17 USB1_ID USB1_ID 0 A Z Z 0 NA NA NA NA Analog VDDA _USB1 27 NA T18 USB1_VBUS USB1_VBUS 0 A Z Z 0 NA N...

Page 47: ...VDDS_DDR VDDS_DDR NA PWR K4 K5 M5 H5 J5 K5 L5 M6 N5 U10 R11 VDDS_OSC VDDS_OSC NA PWR T8 R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR C5 E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR H16 H15 VDDS_PLL_MPU VDDS_PLL_MPU NA PWR C6 D7 VDDS_RTC VDDS_RTC NA PWR C10 E9 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA PWR C12 D10 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA PWR F9 F11 G9 F6 F7 G6 VDD_CORE VDD_CORE NA PWR G11 H7 H8 G...

Page 48: ...SA_ADC VSSA_ADC NA GND P16 M14 N14 VSSA_USB VSSA_USB NA GND V11 V11 VSS_OSC VSS_OSC 28 NA A NA A5 VSS_RTC VSS_RTC 29 NA A A16 A10 WARMRSTn nRESETIN_OUT 0 I OD 0 25 0 PU 11 0 VDDSHV6 Yes 4 PU PD LVCMOS 8 VDDSHV6 C15 A15 XDMA_EVENT_INTR0 xdma_event_intr0 0 I Z 4 9 VDDSHV6 Yes 4 PU PD LVCMOS VDDSHV6 timer4 2 I O clkout1 3 O spi1_cs1 4 I O pr1_pru1_pru_r31_16 5 I EMU2 6 I O gpio0_19 7 I O B15 D14 XDMA...

Page 49: ...ured to multiplex the UART3_TX or UART3_RX signals to this terminal For more details refer to USB GPIO Details section of the AM335x Technical Reference Manual 15 This output should only be used to source the recommended crystal circuit 16 This parameter only applies when this USB PHY terminal is operating in UART2 mode 17 This parameter only applies when this USB PHY terminal is operating in UART...

Page 50: ...ibution network and package When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU 50 Terminal Configuration and Functions Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 51: ...hese valid IO Sets were carefully chosen to provide many possible application scenarios for the user Texas Instruments has developed a Windows based application called Pin Mux Utility that helps a system designer select the appropriate pin multiplexing configuration for their AM335x based product design The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to...

Page 52: ... PIN I O A15 C14 EMU1 MISC EMULATION PIN I O D14 B14 EMU2 MISC EMULATION PIN I O A18 C15 A15 A17 C13 EMU3 MISC EMULATION PIN I O B15 B18 B17 D13 D14 EMU4 MISC EMULATION PIN I O B16 U17 A14 C15 T13 nTRST JTAG TEST RESET ACTIVE LOW I A13 B10 TCK JTAG TEST CLOCK I B14 A12 TDI JTAG TEST DATA INPUT I B13 B11 TDO JTAG TEST DATA OUTPUT O A14 A11 TMS JTAG TEST MODE SELECT I C14 C11 LCD Controller Signals ...

Page 53: ... lcd_data23 LCD data bus O V15 U10 lcd_data3 LCD data bus I O V2 R4 lcd_data4 LCD data bus I O W2 T1 lcd_data5 LCD data bus I O W3 T2 lcd_data6 LCD data bus I O V3 T3 lcd_data7 LCD data bus I O U3 T4 lcd_data8 LCD data bus I O V4 U1 lcd_data9 LCD data bus I O W4 U2 lcd_hsync LCD Horizontal Sync O T7 R5 lcd_memory_clk LCD MCLK O L19 V16 J17 V12 lcd_pclk LCD pixel clock O W5 V5 lcd_vsync LCD Vertica...

Page 54: ...OUTPUT ddr_a8 DDR SDRAM ROW COLUMN ADDRESS O C3 D4 OUTPUT ddr_a9 DDR SDRAM ROW COLUMN ADDRESS O B2 C1 OUTPUT ddr_ba0 DDR SDRAM BANK ADDRESS OUTPUT O A3 C4 ddr_ba1 DDR SDRAM BANK ADDRESS OUTPUT O E1 E1 ddr_ba2 DDR SDRAM BANK ADDRESS OUTPUT O B4 B3 ddr_casn DDR SDRAM COLUMN ADDRESS STROBE O F1 F1 OUTPUT ACTIVE LOW ddr_ck DDR SDRAM CLOCK OUTPUT Differential O C2 D2 ddr_cke DDR SDRAM CLOCK ENABLE OUTP...

Page 55: ... OUTPUT ACTIVE LOW O G2 G2 ddr_vref Voltage Reference Input A H4 J4 ddr_vtp VTP Compensation Resistor I J1 J3 ddr_wen DDR SDRAM WRITE ENABLE OUTPUT O A4 B2 ACTIVE LOW External Memory Interfaces General Purpose Memory Controller Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 gpmc_a0 GPMC Address O U1 R1 R13 gpmc_a1 GPMC Address O U2 U7 R2 U5 V14 gpmc_a10 GPMC Address O...

Page 56: ...O W13 T8 gpmc_ad4 GPMC Address and Data I O V13 U8 gpmc_ad5 GPMC Address and Data I O W14 V8 gpmc_ad6 GPMC Address and Data I O U14 R9 gpmc_ad7 GPMC Address and Data I O W15 T9 gpmc_ad8 GPMC Address and Data I O V15 U10 gpmc_ad9 GPMC Address and Data I O W16 T10 gpmc_advn_ale GPMC Address Valid Address Latch Enable O V10 R7 gpmc_be0n_cle GPMC Byte Enable 0 Command Latch Enable O V8 T6 gpmc_be1n GP...

Page 57: ...27 GPIO I O U12 U12 gpio0_28 GPIO I O L18 K17 gpio0_29 GPIO I O K18 H18 gpio0_3 GPIO I O B18 B17 gpio0_30 GPIO I O R15 T17 gpio0_31 GPIO I O W18 U17 gpio0_4 GPIO I O B17 B16 gpio0_5 GPIO I O A17 A16 gpio0_6 GPIO I O B16 C15 gpio0_7 GPIO I O E18 C18 gpio0_8 GPIO I O V6 V2 gpio0_9 GPIO I O U6 V3 General Purpose IOs GPIO1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 gp...

Page 58: ...o1_9 GPIO I O F18 E17 General Purpose IOs GPIO2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 gpio2_0 GPIO I O U17 T13 gpio2_1 GPIO I O V16 V12 gpio2_10 GPIO I O W2 T1 gpio2_11 GPIO I O W3 T2 gpio2_12 GPIO I O V3 T3 gpio2_13 GPIO I O U3 T4 gpio2_14 GPIO I O V4 U1 gpio2_15 GPIO I O W4 U2 gpio2_16 GPIO I O U5 U3 gpio2_17 GPIO I O V5 U4 gpio2_18 GPIO I O N17 L17 gpio2_1...

Page 59: ...ALL 4 ZCZ BALL 4 3 gpio3_0 GPIO I O J19 H16 gpio3_1 GPIO I O J18 H17 gpio3_10 GPIO I O M19 L18 gpio3_13 GPIO I O NA F15 gpio3_14 GPIO I O NA A13 gpio3_15 GPIO I O NA B13 gpio3_16 GPIO I O NA D12 gpio3_17 GPIO I O NA C12 gpio3_18 GPIO I O NA B12 gpio3_19 GPIO I O NA C13 gpio3_2 GPIO I O K19 J15 gpio3_20 GPIO I O NA D13 gpio3_21 GPIO I O NA A14 gpio3_3 GPIO I O K17 J16 gpio3_4 GPIO I O L19 J17 gpio3...

Page 60: ...10 OSC0_OUT High frequency oscillator output O W12 U11 OSC1_IN Low frequency 32 768 KHz Real Time Clock I A6 A6 oscillator input OSC1_OUT Low frequency 32 768 KHz Real Time Clock O A5 A4 oscillator output PMIC_POWER_EN PMIC_POWER_EN output O C7 C6 porz Active low Power on Reset I E15 B15 RTC_PORz Active low RTC reset input I B7 B5 tclkin Timer Clock In I B15 D14 xdma_event_intr0 External DMA Event...

Page 61: ...AL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 eCAP1_in_PWM1_out Enhanced Capture 1 input or Auxiliary PWM1 I O B16 B19 F17 C15 C16 E16 output eCAP eCAP2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 eCAP2_in_PWM2_out Enhanced Capture 2 input or Auxiliary PWM2 I O C18 E19 C12 C17 E15 output Copyright 2011 2015 Texas Instruments Incorporated Terminal Configuration an...

Page 62: ...p zone input I B17 B16 D12 eHRPWM eHRPWM1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 ehrpwm1A eHRPWM1 A output O U5 U14 U3 ehrpwm1B eHRPWM1 B output O V5 T14 U4 ehrpwm1_tripzone_input eHRPWM1 trip zone input I V4 R13 U1 eHRPWM eHRPWM2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 ehrpwm2A eHRPWM2 A output O U1 V15 R1 U10 ehrpwm2B eHR...

Page 63: ...ZCZ BALL 4 3 eQEP1A_in eQEP1A quadrature input I V6 R14 V2 eQEP1B_in eQEP1B quadrature input I U6 V15 V3 eQEP1_index eQEP1 index I O W6 U15 V4 eQEP1_strobe eQEP1 strobe I O V7 T15 T5 eQEP eQEP2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 eQEP2A_in eQEP2A quadrature input I U13 W2 T1 T12 eQEP2B_in eQEP2B quadrature input I T13 W3 R12 T2 eQEP2_index eQEP2 index I O V...

Page 64: ...er trigger event PWM out I O D19 H19 R19 D17 F17 M18 V8 T6 Timer Timer6 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 timer6 Timer trigger event PWM out I O E17 H18 P17 D18 F18 M17 U8 U6 Timer Timer7 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 timer7 Timer trigger event PWM out I O B15 B19 F19 C16 D14 E18 W9 T7 64 Terminal Configurati...

Page 65: ... O U7 U5 pr1_edio_data_out3 Data Out O T7 R5 pr1_edio_data_out4 Data Out O W5 V5 pr1_edio_data_out5 Data Out O W7 R6 pr1_edio_data_out6 Data Out O V14 V3 T3 U9 pr1_edio_data_out7 Data Out O U15 U3 T4 V9 pr1_edio_latch_in Latch In I B18 B17 pr1_edio_sof Start of Frame O A18 A17 PRU ICSS MDIO Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 pr1_mdio_data MDIO Data I O U17...

Page 66: ...r1_mii1_rxd2 MII Receive Data bit 2 I NA U15 pr1_mii1_rxd3 MII Receive Data bit 3 I NA V15 pr1_mii1_rxdv MII Receive Data Valid I NA T16 pr1_mii1_rxer MII Receive Data Error I NA V17 pr1_mii1_rxlink MII Receive Link I V18 U18 pr1_mii1_txd0 MII Transmit Data bit 0 O NA R14 pr1_mii1_txd1 MII Transmit Data bit 1 O NA T14 pr1_mii1_txd2 MII Transmit Data bit 2 O NA U14 pr1_mii1_txd3 MII Transmit Data b...

Page 67: ...1_pru0_pru_r31_8 PRU0 Data In I H19 F17 pr1_pru0_pru_r31_9 PRU0 Data In I H18 F18 PRU0 General Purpose Outputs Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 pr1_pru0_pru_r30_0 PRU0 Data Out O NA A13 pr1_pru0_pru_r30_1 PRU0 Data Out O NA B13 pr1_pru0_pru_r30_10 PRU0 Data Out O H17 G15 pr1_pru0_pru_r30_11 PRU0 Data Out O G18 G16 pr1_pru0_pru_r30_12 PRU0 Data Out O G19 ...

Page 68: ...4 pr1_pru1_pru_r31_8 PRU1 Data In I U7 U5 pr1_pru1_pru_r31_9 PRU1 Data In I T7 R5 PRU1 General Purpose Outputs Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 pr1_pru1_pru_r30_0 PRU1 Data Out O U1 R1 pr1_pru1_pru_r30_1 PRU1 Data Out O U2 R2 pr1_pru1_pru_r30_10 PRU1 Data Out O W5 V5 pr1_pru1_pru_r30_11 PRU1 Data Out O W7 R6 pr1_pru1_pru_r30_12 PRU1 Data Out O V14 U9 pr1...

Page 69: ...19 V9 W16 L18 T10 V7 mmc1_dat2 MMC SD SDIO Data Bus I O N17 T12 V12 L17 R8 T11 mmc1_dat3 MMC SD SDIO Data Bus I O N16 U12 W13 L16 T8 U12 mmc1_dat4 MMC SD SDIO Data Bus I O U13 V13 T12 U8 mmc1_dat5 MMC SD SDIO Data Bus I O T13 W14 R12 V8 mmc1_dat6 MMC SD SDIO Data Bus I O U14 W17 R9 V13 mmc1_dat7 MMC SD SDIO Data Bus I O V17 W15 T9 U13 mmc1_sdcd SD Card Detect I R15 B13 T17 mmc1_sdwp SD Write Prote...

Page 70: ...7 N18 D17 E16 K15 dcan0_tx DCAN0 Transmit Data O E17 E19 M17 D18 E15 J18 CAN DCAN1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 dcan1_rx DCAN1 Receive Data I C19 F18 G17 D15 E17 G18 dcan1_tx DCAN1 Transmit Data O D18 F19 G19 D16 E18 G17 70 Terminal Configuration and Functions Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Fo...

Page 71: ...3 O M17 J18 gmii1_txen MII Transmit Enable O K17 J16 GEMAC_CPSW MII2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 gmii2_col MII Colision I V18 U18 gmii2_crs MII Carrier Sense I R15 T17 gmii2_rxclk MII Receive Clock I NA T15 gmii2_rxd0 MII Receive Data bit 0 I NA V17 gmii2_rxd1 MII Receive Data bit 1 I NA T16 gmii2_rxd2 MII Receive Data bit 2 I NA U16 gmii2_rxd3 MII ...

Page 72: ...U15 rgmii2_tctl RGMII Transmit Control O NA R13 rgmii2_td0 RGMII Transmit Data bit 0 O NA V15 rgmii2_td1 RGMII Transmit Data bit 1 O NA R14 rgmii2_td2 RGMII Transmit Data bit 2 O NA T14 rgmii2_td3 RGMII Transmit Data bit 3 O NA U14 GEMAC_CPSW RMII1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 rmii1_crs_dv RMII Carrier Sense Data Valid I J18 H17 rmii1_refclk RMII Ref...

Page 73: ...tinued TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 rmii2_txd1 RMII Transmit Data bit 1 O NA R14 rmii2_txen RMII Transmit Enable O NA R13 Copyright 2011 2015 Texas Instruments Incorporated Terminal Configuration and Functions 73 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 74: ...N 2 ZCE BALL 4 ZCZ BALL 4 3 I2C1_SCL I2C1 Clock I OD A17 C19 F18 A16 D15 E17 K19 J15 I2C1_SDA I2C1 Data I OD B17 D18 F19 B16 D16 E18 J18 H17 I2C I2C2 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 I2C2_SCL I2C2 Clock I OD B18 D19 F17 B17 D17 E16 I2C2_SDA I2C2 Data I OD A18 E17 E19 A17 D18 E15 74 Terminal Configuration and Functions Copyright 2011 2015 Texas Instrument...

Page 75: ...M17 U6 V16 C13 J18 V12 V3 mcasp0_fsx McASP0 Transmit Frame Sync I O M19 W4 B13 L18 U16 U2 McASP MCASP1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 mcasp1_aclkr McASP1 Receive Bit Clock I O L18 P18 K17 M16 mcasp1_aclkx McASP1 Transmit Bit Clock I O J18 L19 B12 H17 J17 mcasp1_ahclkr McASP1 Receive Master Clock I O P18 M16 mcasp1_ahclkx McASP1 Transmit Master Clock I ...

Page 76: ... I O A18 A17 SPI SPI1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 spi1_cs0 SPI Chip Select I O E17 E19 F18 C12 D18 E15 K18 E17 H18 spi1_cs1 SPI Chip Select I O C15 D19 E18 A15 C18 D17 F17 E16 spi1_d0 SPI Data I O F19 J18 B13 E18 H17 spi1_d1 SPI Data I O F18 K19 D12 E17 J15 spi1_sclk SPI Clock I O E18 J19 A13 C18 H16 76 Terminal Configuration and Functions Copyright...

Page 77: ... UART Request to Send O B19 W4 C16 U2 uart2_rxd UART Receive Data I A18 G19 J18 A17 G17 H17 N19 K18 uart2_txd UART Transmit Data O B18 G17 K19 B17 G18 J15 M19 L18 UART UART3 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 uart3_ctsn UART Clear to Send I G19 P17 U5 G17 M17 U3 uart3_rtsn UART Request to Send O G17 R19 V5 G18 M18 U4 uart3_rxd UART Receive Data I B16 H17 N...

Page 78: ...NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 uart5_rxd UART Receive Data I J19 P17 W4 H16 M17 U2 V4 W6 uart5_txd UART Transmit Data O K18 L19 R19 H18 J17 M18 V4 U1 78 Terminal Configuration and Functions Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 79: ...o A or Micro B Plug A V19 P16 USB0_VBUS USB0 VBUS A T19 P15 USB USB1 Signals Description TYPE SIGNAL NAME 1 DESCRIPTION 2 ZCE BALL 4 ZCZ BALL 4 3 USB1_CE USB1 Active high Charger Enable output A NA P18 USB1_DM USB1 Data minus A NA R18 USB1_DP USB1 Data plus A NA R17 USB1_DRVVBUS USB1 Active high VBUS control output O NA F15 USB1_ID USB1 OTG ID Micro A or Micro B Plug A NA P17 USB1_VBUS USB1 VBUS A...

Page 80: ... 3 1 1 V Steady state max voltage 0 5 V to IO supply voltage 0 3 V at all IO pins 8 USB0_ID 9 Steady state maximum voltage for the USB ID input 0 5 2 1 V USB1_ID 6 9 Steady state maximum voltage for the USB ID input 0 5 2 1 V Transient overshoot and 25 of corresponding IO supply undershoot specification at voltage for up to 30 of signal IO terminal period Latch up performance 10 Class II 105 C 45 ...

Page 81: ...such they do not have dependencies on the respective IO power supply voltage This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off The USB0_VBUS and USB1_VBUS are the only fail safe IO terminals All other IO terminals are not fail safe and the voltage applied to them should be limited to the value defined by the steady state...

Page 82: ...terms and conditions for TI semiconductor products 5 POH Power on hours when the device is fully functional 5 4 Operating Performance Points OPPs Device OPPs are defined in Table 5 2 through Table 5 9 Table 5 2 VDD_CORE OPPs for ZCZ Package With Device Revision Code Blank 1 VDD_CORE VDD_CORE OPP DDR3 DDR2 2 mDDR 2 L3 and L4 Device Rev DDR3L 2 MIN NOM MAX Blank OPP100 1 056 V 1 100 V 1 144 V 400 MH...

Page 83: ...DDR3 DDR2 2 mDDR 2 L3 and L4 Rev A or DDR3L 2 MIN NOM MAX Newer OPP100 1 056 V 1 100 V 1 144 V 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP50 0 912 V 0 950 V 0 988 V 125 MHz 90 MHz 100 and 50 MHz 1 Frequencies in this table indicate maximum performance for a given OPP condition 2 This parameter represents the maximum memory clock frequency Since data is transferred on both edges of the clock double...

Page 84: ...0 MHz 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP100 1 056 V 1 100 V 1 144 V 300 MHz 400 MHz 266 MHz 200 MHz 200 and 100 MHz OPP50 0 912 V 0 950 V 0 988 V 300 MHz 125 MHz 90 MHz 100 and 50 MHz 1 Frequencies in this table indicate maximum performance for a given OPP condition 2 VDD_MPU is merged with VDD_CORE on the ZCE package 3 This parameter represents the maximum memory clock frequency Since da...

Page 85: ...1 890 V voltage IO domains Supply voltage range for Core VDDS_SRAM_CORE_BG 1 710 1 800 1 890 V SRAM LDOs analog Supply voltage range for MPU VDDS_SRAM_MPU_BB 1 710 1 800 1 890 V SRAM LDOs analog Supply voltage range for DPLL VDDS_PLL_DDR 5 1 710 1 800 1 890 V DDR analog Supply voltage range for DPLL VDDS_PLL_CORE_LCD 5 1 710 1 800 1 890 V CORE and LCD analog Supply voltage range for DPLL VDDS_PLL_...

Page 86: ...e for USB VBUS USB0_VBUS 0 000 5 000 5 250 V comparator input Voltage range for USB VBUS USB1_VBUS 6 0 000 5 000 5 250 V comparator input Voltage range for the USB ID USB0_ID 7 V input Voltage range for the USB ID USB1_ID 6 7 V input Commercial temperature 0 90 Operating temperature Industrial temperature 40 90 C range TJ Extended temperature 40 105 1 The supply voltage defined by OPP100 should be...

Page 87: ...t rating for the system oscillator IOs 5 mA VDDA1P8V_USB0 Maximum current rating for USBPHY 1 8 V 25 mA VDDA1P8V_USB1 4 Maximum current rating for USBPHY 1 8 V 25 mA VDDA3P3V_USB0 Maximum current rating for USBPHY 3 3 V 40 mA VDDA3P3V_USB1 4 Maximum current rating for USBPHY 3 3 V 40 mA VDDA_ADC Maximum current rating for ADC 10 mA VDDSHV1 5 Maximum current rating for dual voltage IO domain 50 mA ...

Page 88: ...ORE 0 95 V nom preserved Cortex A8 Clocks context registers are lost so the Main Oscillator OSC0 OFF application needs to save them to Deepsleep1 the L3 OCMC RAM or DDR before 6 0 10 0 mW All DPLLs are in bypass entering DeepSleep DDR is in self Power domains refresh For wake up boot ROM PD_PER ON executes and branches to system PD_MPU OFF resume PD_GFX OFF PD_WKUP ON DDR is in self refresh Power ...

Page 89: ...teresis voltage at an input N A V VOH High level output voltage driver enabled pullup or IOH 8 mA VDDS_DDR V pulldown disabled 0 4 VOL Low level output voltage driver enabled pullup or IOL 8 mA 0 4 V pulldown disabled Input leakage current Receiver disabled pullup or pulldown inhibited 10 II Input leakage current Receiver disabled pullup enabled 240 80 µA Input leakage current Receiver disabled pu...

Page 90: ...H High level input voltage 2 V VIL Low level input voltage 0 8 V VHYS Hysteresis voltage at an input 0 265 0 44 V VOH High level output voltage driver enabled pullup or IOH 4 mA VDDSHV6 0 45 V pulldown disabled VOL Low level output voltage driver enabled pullup or IOL 4 mA 0 45 V pulldown disabled Input leakage current Receiver disabled pullup or pulldown inhibited 18 II Input leakage current Rece...

Page 91: ...hibited 1 1 µA Input leakage current Receiver disabled pullup enabled 200 40 Input leakage current Receiver disabled pulldown enabled 40 200 XTALIN OSC0 0 65 VIH High level input voltage V VDDS_OSC 0 35 VIL Low level input voltage V VDDS_OSC RTC_XTALIN OSC1 0 65 VIH High level input voltage V VDDS_RTC 0 35 VIL Low level input voltage V VDDS_RTC All other LVCMOS pins VDDSHVx 1 8 V x 1 to 6 VIH High...

Page 92: ...6 mA 0 45 V pulldown disabled Input leakage current Receiver disabled pullup or pulldown inhibited 18 II Input leakage current Receiver disabled pullup enabled 243 100 19 µA Input leakage current Receiver disabled pulldown enabled 51 110 210 IOZ Total leakage current through the terminal connection of a driver receiver 18 µA combination that may include a pullup or pulldown The driver output is di...

Page 93: ... FLOW 2 2 m s 3 RΘJC Junction to case 10 3 10 2 N A RΘJB Junction to board 11 6 12 1 N A RΘJA Junction to free air 24 7 24 2 0 20 5 20 1 1 0 19 7 19 3 2 0 19 2 18 8 3 0 φJT Junction to package top 0 4 0 3 0 0 0 6 0 6 1 0 0 7 0 7 2 0 0 9 0 8 3 0 φJB Junction to board 11 9 12 7 0 0 11 7 12 3 1 0 11 7 12 3 2 0 11 6 12 2 3 0 1 These values are based on a JEDEC defined 2S2P system with the exception of...

Page 94: ...oltage Decoupling Characteristics PARAMETER TYP UNIT CVDD_CORE 1 10 08 μF CVDD_MPU 2 3 10 05 μF 1 The typical value corresponds to 1 cap of 10 μF and 8 caps of 10 nF 2 Not available on the ZCE package VDD_MPU is merged with VDD_CORE on the ZCE package 3 The typical value corresponds to 1 cap of 10 μF and 5 caps of 10 nF 5 9 1 2 IO and Analog Voltage Decoupling Capacitors Table 5 14 summarizes the ...

Page 95: ... voltage drop on the VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals A 10 µF is recommended to be placed close to the terminal and routed with widest traces possible to minimize the voltage drop on VDDS_SRAM_MPU_BB terminals 6 Typical values consist of 1 cap of 10 μF and 2 caps of 10 nF 7 Typical values consist of 1 cap of 10 μF and 6 caps of 10 ...

Page 96: ...USB VDDA_1P8V_USBx CVDDA_1P8V_USBx VSSA_USB ADC VDDA_ADC CVDDA_ADC VSSA_ADC VDDS_OSC CVDDS_OSC RTC CAP_VDD_RTC CCAP_VDD_RTC VDDSHV1 IOs CVDDSHV1 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com Figure 5 1 shows an example of the external capacitors A Decoupling capacitors must be placed as closed as possible to the power terminal Choose the ground located...

Page 97: ...rence VREFN VREFP Internal voltage reference Differential non linearity VDDA_ADC 1 8 V 1 0 5 1 LSB DNL External voltage reference VREFP VREFN 1 8 V Source impedance 50 Ω Internal voltage reference VDDA_ADC 1 8 V 2 1 2 LSB External voltage reference VREFP VREFN 1 8 V Integral non linearity INL Source impedance 1 kΩ Internal voltage reference VDDA_ADC 1 8 V 1 LSB External voltage reference VREFP VRE...

Page 98: ...put frequency 1 65 97 10 12 ƒ Ω AIN 7 0 2 Sampling Dynamics ADC Conversion time 15 clock cycles ADC Acquisition time 2 clock cycles Sampling rate ADC clock 3 MHz 200 kSPS Channel to channel isolation 100 dB Touch Screen Switch Drivers Pull up and pull down switch ON resistance Ron 2 Ω Pull up and pull down Source impedance 500 Ω 0 5 uA switch current leakage Ileak Drive current 25 mA Touch screen ...

Page 99: ...ing range of the internal ESD protection devices it is recommended to limit the maximum slew rate for powering on the supplies to be less than 1 0E 5 V s For instance as shown in Figure 6 1 TI recommends to have the supply ramp slew for a 1 8 V supply be greater than 18 µs Figure 6 1 Power Supply Slew and Slew Rate Copyright 2011 2015 Texas Instruments Incorporated Power and Clocking 99 Submit Doc...

Page 100: ...ive VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground D If the system uses mDDR or DDR2 memory devices VDDS_DDR can be ramped simultaneously with the other 1 8 V IO power supplies E VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not requ...

Page 101: ...he ZCE package option has the VDD_MPU domain merged with the VDD_CORE domain D If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground E If the system uses mDDR or ...

Page 102: ...spective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground D If the system uses mDDR or DDR2 memory devices VDDS_DDR can be ramped simultaneously with the other 1 8 V IO power supplies E VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not...

Page 103: ...D If a USB port is not used the respective VDDA1P8V_USB terminal may be connected to any 1 8 V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3 3 V power supply If the system does not have a 3 3 V power supply the VDDA3P3V_USB terminal may be connected to ground E If the system uses mDDR or DDR2 memory devices VDDS_DDR can be ramped simultaneously with the other 1 8 ...

Page 104: ...ctionality is not required If CAP_VDD_RTC is ramped after VDD_CORE there might be a small amount of additional leakage current on VDD_CORE The power sequence shown provides the lowest leakage option F To configure VDDSHVx 1 6 as 1 8 V power up the respective VDDSHVx 1 6 to 1 8 V following the recommended sequence To configure VDDSHVx 1 6 as 3 3 V power up the respective VDDSHVx 1 6 to 3 3 V follow...

Page 105: ...2015 If none of the VDDSHVx 1 6 power supplies are configured as 3 3 V the VDDS power supply may ramp down along with the VDDSHVx 1 6 supplies or after all the VDDSHVx 1 6 supplies have ramped down It is recommended to maintain VDDS 1 5V as all the other supplies fully ramp down to minimize in rush currents 6 1 3 VDD_MPU_MON Connections Figure 6 7 shows the VDD_MPU_MON connectivity VDD_MPU_MON con...

Page 106: ...requirements for the DPLL Figure 6 8 DPLL Power Supply Connectivity Table 6 1 DPLL Power Supply Requirements SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT VDDA1P8V_USB0 Supply voltage range for USBPHY and PER DPLL Analog 1 8 V 1 71 1 8 1 89 V Max peak to peak supply noise 50 mV p p VDDS_PLL_MPU Supply voltage range for DPLL MPU analog 1 71 1 8 1 89 V Max peak to peak supply noise 50 mV p p VDDS_PLL_COR...

Page 107: ...Hz reference clock which is used to clock all non RTC functions and is connected to the XTALIN and XTALOUT terminals This clock source is referred to as the master oscillator CLK_M_OSC in the AM335x Sitara Processors Technical Reference Manual SPRUH73 OSC0 is enabled by default after power is applied For more information related to recommended circuit topologies and crystal oscillator circuit requ...

Page 108: ...Figure 6 9 OSC0 Crystal Circuit Schematic Table 6 2 OSC0 Crystal Circuit Requirements PARAMETER MIN TYP MAX UNIT ƒxtal Crystal parallel resonance Fundamental mode oscillation only 19 2 24 MHz frequency 25 or 26 Crystal frequency stability 50 50 ppm and tolerance 1 Cshunt 5 pF 12 24 CC1 C1 capacitance pF Cshunt 5 pF 18 24 Cshunt 5 pF 12 24 CC2 C2 capacitance pF Cshunt 5 pF 18 24 Cshunt Shunt capaci...

Page 109: ...e ZCZ package 0 01 pF Pxtal The actual values of the ESR ƒxtal and CL should be used to yield a Pxtal 0 5 ESR 2 π ƒxtal typical crystal power dissipation value Using the maximum values CL VDDS_OSC 2 specified for ESR ƒxtal and CL parameters yields a maximum power dissipation value tsX Start up time 1 5 ms Figure 6 10 OSC0 Start Up Time Copyright 2011 2015 Texas Instruments Incorporated Power and C...

Page 110: ...ility and tolerance 1 50 50 ppm tdc XTALIN Duty cycle LVCMOS reference clock period 45 55 tjpp XTALIN Jitter peak to peak LVCMOS reference clock period 1 1 tR XTALIN Time LVCMOS reference clock rise 5 ns tF XTALIN Time LVCMOS reference clock fall 5 ns 1 Initial accuracy temperature drift and aging effects should be combined when evaluating a reference clock for this requirement 6 2 2 3 OSC1 Intern...

Page 111: ...ALIN and RTC_XTALOUT signals For recommended values of crystal circuit components see Table 6 5 Figure 6 12 OSC1 ZCE Package Crystal Circuit Schematic A Oscillator components Crystal C1 C2 optional Rbias and Rd must be located close to the AM335x package Parasitic capacitance to the printed circuit board PCB ground and other signals should be minimized to reduce noise coupled into the oscillator V...

Page 112: ...s nominal 80 kΩ resistance negative resistance of 725 kΩ and worst case negative resistance of 250 kΩ 1 Initial accuracy temperature drift and aging effects should be combined when evaluating a reference clock for this requirement Table 6 6 OSC1 Crystal Circuit Characteristics NAME DESCRIPTION MIN TYP MAX UNIT Cpkg Shunt capacitance of ZCE package 0 17 pF package ZCZ package 0 01 pF Pxtal The actu...

Page 113: ... couple noise into OSC1 via the RTC_XTALOUT terminal The RTC_XTALIN terminal has a 10 to 40 kΩ internal pullup resistor which is enabled when OSC1 is disabled This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer Figure 6 15 OSC1 ZCE Package LVCMOS Circuit Schematic Figure 6 16 OSC1 ZCZ...

Page 114: ...ternal 10 kΩ pull up on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an invalid logic level which may increase leakage current through the oscillator input buffer OSC1 is disabled by default after power is applied Therefore both RTC_XTALIN and RTC_XTALOUT terminals should be a no connect NC when OSC1 is not used Figure 6 17 OSC1 ZCE Package Not ...

Page 115: ...talk into the clock circuits Therefore there are no plans to specify jitter performance for these outputs 6 2 4 1 CLKOUT1 The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal This terminal connects to one of seven internal signals via configurable multiplexers The XDMA_EVENT_INTR0 multiplexer must be configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal ...

Page 116: ...ot include delays by board routings As a good board design practice such delays must always be taken into account Timing values may be adjusted by increasing or decreasing such delays TI recommends utilizing the available IO buffer information specification IBIS models to analyze the timing characteristics correctly If needed external logic hardware such as buffers may be used to compensate any ti...

Page 117: ... baud Maximum programmable baud rate 1 Mbps 1 tw RX Pulse duration receive data bit H 2 1 H 2 1 ns 1 H Period of baud rate 1 programmed baud rate Table 7 2 Switching Characteristics for DCANx Transmit see Figure 7 1 NO PARAMETER MIN MAX UNIT ƒbaud baud Maximum programmable baud rate 1 Mbps 2 tw TX Pulse duration transmit data bit H 2 1 H 2 1 ns 1 H Period of baud rate 1 programmed baud rate Figure...

Page 118: ...4P 1 1 ns 1 P Period of PICLKOCP interface clock Table 7 4 Switching Characteristics for DMTimer 4 7 see Figure 7 2 NO PARAMETER MIN MAX UNIT 2 tw TIMERxH Pulse duration high 4P 3 1 ns 3 tw TIMERxL Pulse duration low 4P 3 1 ns 1 P Period of PICLKTIMER functional clock Figure 7 2 Timer Timing 118 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentat...

Page 119: ... documents that describe the Ethernet switch reference these signals by their internal signal name For a cross reference of internal signal names to terminal names see Table 4 1 Operation of the EMAC and switch is not supported for OPP50 Table 7 5 EMAC and Switch Timing Conditions PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1 1 5 1 ns tF Input signal fall time 1 1 5 1 ns ...

Page 120: ... and Switch MII Electrical Data and Timing Table 7 9 Timing Requirements for GMII x _RXCLK MII Mode see Figure 7 6 10 Mbps 100 Mbps NO UNIT MIN TYP MAX MIN TYP MAX 1 tc RX_CLK Cycle time RX_CLK 399 96 400 04 39 996 40 004 ns 2 tw RX_CLKH Pulse duration RX_CLK high 140 260 14 26 ns 3 tw RX_CLKL Pulse duration RX_CLK low 140 260 14 26 ns 4 tt RX_CLK Transition time RX_CLK 5 5 ns Figure 7 6 GMII x _R...

Page 121: ...Timing MII Mode Table 7 11 Timing Requirements for GMII x _RXD 3 0 GMII x _RXDV and GMII x _RXER MII Mode see Figure 7 8 10 Mbps 100 Mbps NO UNIT MIN TYP MAX MIN TYP MAX tsu RXD RX_CLK Setup time RXD 3 0 valid before RX_CLK 1 tsu RX_DV RX_CLK Setup time RX_DV valid before RX_CLK 8 8 ns tsu RX_ER RX_CLK Setup time RX_ER valid before RX_CLK th RX_CLK RXD Hold time RXD 3 0 valid after RX_CLK 2 th RX_...

Page 122: ...de see Figure 7 9 10 Mbps 100 Mbps NO PARAMETER UNIT MIN TYP MAX MIN TYP MAX td TX_CLK TXD Delay time TX_CLK high to TXD 3 0 valid 1 5 25 5 25 ns td TX_CLK TX_EN Delay time TX_CLK to TX_EN valid Figure 7 9 GMII x _TXD 3 0 GMII x _TXEN Timing MII Mode 122 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 A...

Page 123: ... Mode Table 7 14 Timing Requirements for RMII x _RXD 1 0 RMII x _CRS_DV and RMII x _RXER RMII Mode see Figure 7 11 NO MIN TYP MAX UNIT tsu RXD REF_CLK Setup time RXD 1 0 valid before REF_CLK 1 tsu CRS_DV REF_CLK Setup time CRS_DV valid before REF_CLK 4 ns tsu RX_ER REF_CLK Setup time RX_ER valid before REF_CLK th REF_CLK RXD Hold time RXD 1 0 valid after REF_CLK 2 th REF_CLK CRS_DV Hold time CRS_D...

Page 124: ...EF_CLK TXD Delay time REF_CLK high to TXD 1 0 valid 1 2 13 ns td REF_CLK TXEN Delay time REF_CLK to TXEN valid tr TXD Rise time TXD outputs 2 1 5 ns tr TX_EN Rise time TX_EN output tf TXD Fall time TXD outputs 3 1 5 ns tf TX_EN Fall time TX_EN output Figure 7 12 RMII x _TXD 1 0 RMII x _TXEN Timing RMII Mode 124 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated S...

Page 125: ...etup time RD 3 0 valid tsu RD RXC 1 1 1 before RXC high or low 1 ns Setup time RX_CTL valid tsu RX_CTL RXC 1 1 1 before RXC high or low Hold time RD 3 0 valid after th RXC RD 1 1 1 RXC high or low 2 ns Hold time RX_CTL valid after th RXC RX_CTL 1 1 1 RXC high or low tt RD Transition time RD 0 75 0 75 0 75 3 ns tt RX_CTL Transition time RX_CTL 0 75 0 75 0 75 A RGMII x _RCLK must be externally delay...

Page 126: ...IN TYP MAX tsk TD TXC TD to TXC output skew 0 5 0 5 0 5 0 5 0 5 0 5 1 ns tsk TX_CTL TXC TX_CTL to TXC output skew 0 5 0 5 0 5 0 5 0 5 0 5 tt TD Transition time TD 0 75 0 75 0 75 2 ns tt TX_CTL Transition time TX_CTL 0 75 0 75 0 75 A The EMAC and switch implemented in the AM335x device supports internal delay mode but timing closure was not performed for this mode of operation Therefore the AM335x ...

Page 127: ...NOR Flash Timing Conditions Synchronous Mode PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1 5 ns tF Input signal fall time 1 5 ns Output Condition CLOAD Output load capacitance 3 30 pF Table 7 21 GPMC and NOR Flash Timing Requirements Synchronous Mode OPP100 OPP50 NO UNIT MIN MAX MIN MAX F12 tsu dV clkH Setup time input data gpmc_ad 15 0 valid before output clock 3 2 13 2 ...

Page 128: ...falling edge to D 4 2 3 D 4 1 9 D 4 3 3 D 4 6 9 ns gpmc_nbe0_cle gpmc_nbe1 invalid 12 F7 td clkL be x nIV Delay time gpmc_clk falling edge to D 4 2 3 D 4 1 9 D 4 3 3 D 4 11 9 ns gpmc_nbe0_cle gpmc_nbe1 invalid 13 F8 td clkH advn Delay time output clock gpmc_clk rising edge to G 7 2 3 G 7 4 5 G 7 3 3 G 7 9 5 ns output address valid and address latch enable gpmc_advn_ale transition F9 td clkH advnIV...

Page 129: ...ider 0 F 0 5 CSExtraDelay GPMC_FCLK 17 Case GpmcFCLKDivider 1 F 0 5 CSExtraDelay GPMC_FCLK 17 if ClkActivationTime and CSOnTime are odd or ClkActivationTime and CSOnTime are even F 1 0 5 CSExtraDelay GPMC_FCLK 17 otherwise Case GpmcFCLKDivider 2 F 0 5 CSExtraDelay GPMC_FCLK 17 if CSOnTime ClkActivationTime is a multiple of 3 F 1 0 5 CSExtraDelay GPMC_FCLK 17 if CSOnTime ClkActivationTime 1 is a mu...

Page 130: ...0 5 WEExtraDelay GPMC_FCLK 17 if ClkActivationTime and WEOnTime are odd or ClkActivationTime and WEOnTime are even I 1 0 5 WEExtraDelay GPMC_FCLK 17 otherwise Case GpmcFCLKDivider 2 I 0 5 WEExtraDelay GPMC_FCLK 17 if WEOnTime ClkActivationTime is a multiple of 3 I 1 0 5 WEExtraDelay GPMC_FCLK 17 if WEOnTime ClkActivationTime 1 is a multiple of 3 I 2 0 5 WEExtraDelay GPMC_FCLK 17 if WEOnTime ClkAct...

Page 131: ...7 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 17 GPMC and NOR Flash Synchronous Single Read GpmcFCLKDivider 0 Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 131 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM...

Page 132: ...3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 18 GPMC and NOR Flash Synchronous Burst Read 4x16 bit GpmcFCLKDivider 0 132 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM335...

Page 133: ...3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 19 GPMC and NOR Flash Synchronous Burst Write GpmcFCLKDivider 0 Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 133 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357...

Page 134: ...3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 20 GPMC and Multiplexed NOR Flash Synchronous Burst Read 134 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357...

Page 135: ...5 0 F14 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 B In gpmc_wait x x is equal to 0 or 1 Figure 7 21 GPMC and Multiplexed NOR Flash Synchronous Burst Write Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 135 Submit Documentation Feedback Product Folder Links AM3359 AM...

Page 136: ...LK 3 FI4 Delay time output address gpmc_a 27 1 generation from internal functional clock 6 5 6 5 ns GPMC_FCLK 3 FI5 Delay time output address gpmc_a 27 1 valid from internal functional clock 6 5 6 5 ns GPMC_FCLK 3 FI6 Delay time output lower byte enable and command latch enable gpmc_be0n_cle 6 5 6 5 ns output upper byte enable gpmc_be1n generation from internal functional clock GPMC_FCLK 3 FI7 Del...

Page 137: ...0 2 2 ns tF d Fall time output data gpmc_ad 15 0 2 2 ns FA0 tw be x nV Pulse duration output lower byte Read N 12 N 12 ns enable and command latch enable Write N 12 N 12 gpmc_be0n_cle output upper byte enable gpmc_be1n valid time FA1 tw csnV Pulse duration output chip select Read A 1 A 1 ns gpmc_csn x 13 low Write A 1 A 1 FA3 td csnV advnIV Delay time output chip select Read B 2 0 2 B 2 2 0 B 2 5 ...

Page 138: ...ffTime CSOnTime TimeParaGranularity 1 0 5 ADVExtraDelay CSExtraDelay GPMC_FCLK 14 3 C OEOffTime CSOnTime TimeParaGranularity 1 0 5 OEExtraDelay CSExtraDelay GPMC_FCLK 14 4 D PageBurstAccessTime TimeParaGranularity 1 GPMC_FCLK 14 5 E WEOnTime CSOnTime TimeParaGranularity 1 0 5 WEExtraDelay CSExtraDelay GPMC_FCLK 14 6 F WEOffTime CSOnTime TimeParaGranularity 1 0 5 WEExtraDelay CSExtraDelay GPMC_FCLK...

Page 139: ...ime required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input data will be internally sampled by active functional clock edge FA5 value must be stored inside AccessTime register bits field C GPMC_FCLK is an internal clock GPMC functional clock not provided externally Figure 7 22 GPMC and N...

Page 140: ... parameter illustrates amount of time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input data will be internally sampled by active functional clock edge FA5 value must be stored inside AccessTime register bits field C GPMC_FCLK is an internal clock GPMC functional clock not provided...

Page 141: ... FA21 calculation must be stored inside AccessTime register bits field C FA20 parameter illustrates amount of time required to internally sample successive input page data It is expressed in number of GPMC functional clock cycles After each access to input page data next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles FA20 is also the d...

Page 142: ...AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 Figure 7 25 GPMC and NOR Flash Asynchronous Write Single Word 142 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3...

Page 143: ...f time required to internally sample input data It is expressed in number of GPMC functional clock cycles From start of read cycle and after FA5 functional clock cycles input data will be internally sampled by active functional clock edge FA5 value must be stored inside AccessTime register bits field C GPMC_FCLK is an internal clock GPMC functional clock not provided externally Figure 7 26 GPMC an...

Page 144: ...3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 Figure 7 27 GPMC and Multiplexed NOR Flash Asynchronous Write Single Word 144 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 ...

Page 145: ...ctional clock GPMC_FCLK 3 GNFI6 Delay time output enable gpmc_oen generation from internal functional 6 5 6 5 ns clock GPMC_FCLK 3 GNFI7 Delay time output write enable gpmc_wen generation from internal 6 5 6 5 ns functional clock GPMC_FCLK 3 GNFI8 Skew functional clock GPMC_FCLK 3 100 100 ps 1 Internal parameters table must be used to calculate data access time stored in the corresponding CS regis...

Page 146: ...lid to output address valid and address latch enable gpmc_advn_ale invalid GNF9 tc wen Cycle time write H 8 H 8 ns GNF10 td csnV oenV Delay time output chip select gpmc_csn x 13 I 9 0 2 I 9 2 0 I 9 5 I 9 5 ns valid to output enable gpmc_oen valid GNF13 tw oenV Pulse duration output enable gpmc_oen valid K 10 K 10 ns GNF14 tc oen Cycle time read L 11 L 11 ns GNF15 tw oenIV csnIV Delay time output e...

Page 147: ...M3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 1 In gpmc_csn x x is equal to 0 1 2 3 4 or 5 Figure 7 28 GPMC and NAND Flash Command Latch Cycle 1 In gpmc_csn x x is equal to 0 1 2 3 4 or 5 Figure 7 29 GPMC and NAND Flash Address Latch Cycle Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 147 Submit Documentation Feedback Pr...

Page 148: ...art of read cycle and after GNF12 functional clock cycles input data will be internally sampled by active functional clock edge GNF12 value must be stored inside AccessTime register bits field 2 GPMC_FCLK is an internal clock GPMC functional clock not provided externally 3 In gpmc_csn x x is equal to 0 1 2 3 4 or 5 In gpmc_wait x x is equal to 0 or 1 Figure 7 30 GPMC and NAND Flash Data Read Cycle...

Page 149: ... determine the maximum clock period see the respective LPDDR memory data sheet Figure 7 32 LPDDR Memory Interface Clock Timing 7 7 2 1 2 LPDDR Interface This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing specification The design rules constrain PCB trace length PCB trace skew signal integrity cross talk and signal timing These rules when follow...

Page 150: ... T NC A NC A NC AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A Enable internal weak pulldown on these pins For details see the EMIF section of the AM335x Sitara Processors Technical Reference Manual SPRUH73 B For all the termination requirements see Section 7 7 2 1 2 9 Figure 7 33 16 Bit LPDDR Interface Using One 16 Bit LPDDR Device 150 Peripheral Inf...

Page 151: ...period selected for the AM335x LPDDR interface 7 7 2 1 2 3 PCB Stackup The minimum stackup required for routing the AM335x device is a four layer stackup as shown in Table 7 33 Additional layers may be added to the PCB stackup to accommodate other circuitry enhance signal integrity and electromagnetic interference performance or to reduce the size of the PCB footprint Table 7 33 Minimum PCB Stacku...

Page 152: ... BGA escape via hole size 2 10 mils 11 Single ended impedance Zo 3 50 75 Ω 12 Impedance control 4 5 Zo 5 Zo Zo 5 Ω 1 For the LPDDR device BGA pad size see the LPDDR device manufacturer documentation 2 A 20 10 via may be used if enough power routing resources are available An 18 10 via allows for more flexible power routing to the AM335x device 3 Zo is the nominal singled ended impedance selected f...

Page 153: ...x Device and LPDDR Device Placement Table 7 35 Placement Specifications 1 NO PARAMETER MIN MAX UNIT 1 X 2 3 1750 mils 2 Y 2 3 1280 mils 3 Y Offset 2 3 4 650 mils 4 Clearance from non LPDDR signal to LPDDR keepout region 5 6 4 w 1 LPDDR keepout region to encompass entire LPDDR routing area 2 For dimension definitions see Figure 7 34 3 Measurements from center of AM335x device to center of LPDDR dev...

Page 154: ... Keepout Region 7 7 2 1 2 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry Table 7 36 contains the minimum numbers and capacitance required for the bulk bypass capacitors Note that this table only covers the bypass needs of the AM335x LPDDR interface and LPDDR devices Additional bulk bypass capacitance may be needed for othe...

Page 155: ...335x VDDS_DDR HS bypass capacitor count 3 10 Devices 10 AM335x VDDS_DDR HS bypass capacitor total capacitance 0 6 μF 11 LPDDR device HS bypass capacitor count 3 4 8 Devices 12 LPDDR device HS bypass capacitor total capacitance 4 0 4 μF 1 LxW 10 mil units for example a 0402 is a 40x20 mil surface mount capacitor 2 An additional HS bypass capacitor can share the connection vias only if it is mounted...

Page 156: ...the AM335x device Table 7 40 shows the specifications for the serial terminators in such cases Table 7 40 LPDDR Signal Terminations NO PARAMETER MIN TYP MAX UNIT 1 CK net class 1 0 22 Zo 2 Ω 2 ADDR_CTRL net class 1 3 4 0 22 Zo 2 Ω 3 DQS0 DQS1 DQ0 and DQ1 net classes 0 22 Zo 2 Ω 1 Only series termination is permitted 2 Zo is the LPDDR PCB trace characteristic impedance 3 Series termination values l...

Page 157: ...TRL to CK skew length mismatch 100 mils 7 ADDR_CTRL to ADDR_CTRL skew length mismatch 100 mils 8 Center to center ADDR_CTRL to other LPDDR trace spacing 4 4w 9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing 4 3w 10 ADDR_CTRL A to B and ADDR_CTRL A to C skew length mismatch 2 100 mils 11 ADDR_CTRL B to C skew length mismatch 100 mils 1 CK represents the clock net class and ADDR_CTRL re...

Page 158: ... 100 mils 6 Center to center DQ x to other LPDDR trace spacing 2 4 4w 7 Center to center DQ x to other DQ x trace spacing 2 5 3w 1 DQS x represents the DQS0 and DQS1 clock net classes and DQ x represents the DQ0 and DQ1 signal net classes 2 Center to center spacing is allowed to fall to minimum w for up to 500 mils of routed length to accommodate BGA escape and routing congestion 3 There is no req...

Page 159: ...llowed result in a reliable DDR2 memory system without the need for a complex timing closure process For more information regarding the guidelines for using this DDR2 specification see the Understanding TI s PCB Routing Rule Based DDR Timing Specification application report SPRAAV0 This application report provides generic guidelines and approach All the specifications provided in the data manual t...

Page 160: ...x T T T T T T T T T T T AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface B One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin C For all the termination requirements see Section 7 7 2 2 2 9 Figure 7 39 16 Bit DDR2 Inter...

Page 161: ...A0 A15 CS CAS RAS WE CKE CK CK VREF ODT 0 1 µF B AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface B One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin C For all the termination requirements see Section 7 7 2 2 2 9 Figu...

Page 162: ...ility 3 92 terminal devices are also supported for legacy reasons New designs will migrate to 84 terminal DDR2 devices Electrically the 92 and 84 terminal DDR2 devices are the same 7 7 2 2 2 3 PCB Stackup The minimum stackup required for routing the AM335x device is a four layer stackup as shown in Table 7 45 Additional layers may be added to the PCB stackup to accommodate other circuitry enhance ...

Page 163: ...BGA escape via hole size 2 10 mils 11 Single ended impedance Zo 3 50 75 Ω 12 Impedance control 4 5 Zo 5 Zo Zo 5 Ω 1 For the DDR2 device BGA pad size see the DDR2 device manufacturer documentation 2 A 20 10 via may be used if enough power routing resources are available An 18 10 via allows for more flexible power routing to the AM335x device 3 Zo is the nominal singled ended impedance selected for ...

Page 164: ...x Device and DDR2 Device Placement Table 7 47 Placement Specifications 1 NO PARAMETER MIN MAX UNIT 1 X 2 3 1750 mils 2 Y 2 3 1280 mils 3 Y Offset 2 3 4 650 mils 4 Clearance from non DDR2 signal to DDR2 keepout region 5 6 4 w 1 DDR2 keepout region to encompass entire DDR2 routing area 2 For dimension definitions see Figure 7 41 3 Measurements from center of AM335x device to center of DDR2 device 4 ...

Page 165: ...7 7 2 2 2 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry Table 7 48 contains the minimum numbers and capacitance required for the bulk bypass capacitors Note that this table only covers the bypass needs of the AM335x DDR2 interface and DDR2 devices Additional bulk bypass capacitance may be needed for other circuitry Table 7...

Page 166: ...pacitor count 3 10 devices 10 AM335x VDDS_DDR HS bypass capacitor total capacitance 0 6 μF 11 DDR2 device HS bypass capacitor count 3 4 8 devices 12 DDR2 device HS bypass capacitor total capacitance 4 0 4 μF 1 LxW 10 mil units for example a 0402 is a 40x20 mil surface mount capacitor 2 An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the...

Page 167: ...used for these net classes If the DDR2 interface is operated at a lower frequency 200 MHz clock rate on device terminations are not specifically required for the DQS x and DQ x net class signals and serial terminations for the CK and ADDR_CTRL net class signals are not mandatory System designers may evaluate the need for serial terminators for EMI and overshoot reduction Placement of serial termin...

Page 168: ...0 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 7 39 and Figure 7 40 TI does not recommend other methods of creating DDR_VREF Figure 7 43 shows the layout guidelines for DDR_VREF Figure 7 43 DDR_VR...

Page 169: ... mils 8 Center to center ADDR_CTRL to other DDR2 trace spacing 4 4w 9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing 4 3w 10 ADDR_CTRL A to B and ADDR_CTRL A to C skew length mismatch 2 100 mils 11 ADDR_CTRL B to C skew length mismatch 100 mils 1 CK represents the clock net class and ADDR_CTRL represents the address and control signal net class 2 Series terminator if used should be lo...

Page 170: ...the DQS0 and DQS1 clock net classes and DQ x represents the DQ0 and DQ1 signal net classes 2 Differential impedance should be Zo x 2 where Zo is the single ended impedance defined in Table 7 46 3 Center to center spacing is allowed to fall to minimum w for up to 500 mils of routed length to accommodate BGA escape and routing congestion 4 There is no requirement for skew matching between data bytes...

Page 171: ...MHz Figure 7 46 DDR3 Memory Interface Clock Timing 7 7 2 3 1 1 DDR3 versus DDR2 This specification only covers AM335x PCB designs that utilize DDR3 memory Designs using DDR2 memory should use the DDR2 routing guidleines described in Section 7 7 2 2 While similar the two memory systems have different requirements It is currently not possible to design one PCB that meets the requirements of both DDR...

Page 172: ...data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 interface operation 7 7 2 3 3 1 DDR3 Interface Schematic The DDR3 interface schematic varies depending upon the width of the DDR3 devices used Figure 7 47 shows the schematic connections for 16 bit interface on AM335x device using one x16 DDR3 device and Figure 7 49 shows the schematic connections fo...

Page 173: ... CS A0 A15 CAS RAS WE RESET CKE ZQ VREFDQ VREFCA ZQ Zo Zo Zo Zo DDR_VREF DDR_VTT VDDS_DDR Termination is required See terminator comments Zo Value determined according to the DDR3 memory device data sheet ZQ 0 1 µF AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 Figure 7 47 16 Bit DDR3 Interface Using One 16 Bit DDR3 Device with VTT Termination Copyright...

Page 174: ...SET CKE ZQ VREFDQ VREFCA ZQ Value determined according to the DDR3 memory device data sheet ZQ 1 K Ω 1 VDDS_DDR A 0 1 µF 0 1 µF 1 K Ω 1 DDR_VREF AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A VDDS_DDR is the power supply for the DDR3 memories and the AM335x DDR3 interface Figure 7 48 16 Bit DDR3 Interface Using One 16 Bit DDR3 Device without VTT Termi...

Page 175: ...2 CS A0 A15 CAS RAS WE RESET CKE ZQ VREFDQ VREFCA Termination is required See terminator comments Zo Value determined according to the DDR3 memory device data sheet ZQ 0 1 µF ZQ Zo Zo Zo Zo DDR_VREF DDR_VTT VDDS_DDR TDQS NC NC TDQS 0 1 µF DM TDQS DDR_DQM1 DM TDQS DDR_DQM0 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 Figure 7 49 16 Bit DDR3 Interface U...

Page 176: ...he DDR3 interface is a four layer stack up as shown in Table 7 59 Additional layers may be added to the PCB stackup to accommodate other circuitry enhance signal integrity and electromagnetic interference performance or to reduce the size of the PCB footprint Table 7 59 Minimum PCB Stackup 1 LAYER TYPE DESCRIPTION 1 Signal Top signal routing 2 Plane Ground 3 Plane Split Power Plane 4 Signal Bottom...

Page 177: ...ference layer return current as the trace routes switch routing layers 3 No traces should cross reference plane cuts within the DDR3 routing region High speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation 4 Reference planes are to be directly adjacent to the signal plane to minimize the size of the return curre...

Page 178: ...Specifications 1 NO PARAMETER MIN MAX UNIT 1 X1 2 3 4 1000 mils 2 X2 2 3 600 mils 3 Y Offset 2 3 4 1500 mils 4 Clearance from non DDR3 signal to DDR3 keepout region 5 6 4 w 1 DDR3 keepout region to encompass entire DDR3 routing area 2 For dimension definitions see Figure 7 50 3 Measurements from center of AM335x device to center of DDR3 device 4 Minimizing X1 and Y improves timing margins 5 w is d...

Page 179: ...gion 7 7 2 3 3 6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry Table 7 62 contains the minimum numbers and capacitance required for the bulk bypass capacitors Note that this table only covers the bypass needs of the AM335x DDR3 interface and DDR3 devices Additional bulk bypass capacitance may be needed for other circuitry Ta...

Page 180: ...citor connect to connection via 2 8 35 100 mils 11 Number of connection vias for each DDR3 device power and ground 1 vias terminal 9 12 Trace length from DDR3 device power and ground terminal to connection 35 60 mils via 2 7 1 LxW 10 mil units for example a 0402 is a 40x20 mil surface mount capacitor 2 Closer and shorter is better 3 Measured from the nearest AM335x VDDS_DDR and ground terminal to ...

Page 181: ... using specific PCB design details before implementing this topology 7 7 2 3 3 10 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x device DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a voltage divider connected to the VDDS_DDR power supply It should be routed as a nominal 20 mil wide tr...

Page 182: ...side of the PCB or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB 7 7 2 3 4 1 1 CK and ADDR_CTRL Topologies Two DDR3 Devices Figure 7 52 shows the topology of the CK net classes and Figure 7 53 shows the topology for the corresponding ADDR_CTRL net classes Figure 7 52 CK Topology for Two DDR3 Devices Figure 7 53 ADDR_CTR...

Page 183: ...RS717H OCTOBER 2011 REVISED MAY 2015 Figure 7 54 CK Routing for Two Single Side DDR3 Devices Figure 7 55 ADDR_CTRL Routing for Two Single Side DDR3 Devices Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 183 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 184: ...d routing and assembly complexity Figure 7 56 and Figure 7 57 show the routing for CK and ADDR_CTRL respectively for two DDR3 devices mirrored in a single pair configuration Figure 7 56 CK Routing for Two Mirrored DDR3 Devices Figure 7 57 ADDR_CTRL Routing for Two Mirrored DDR3 Devices 184 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Fe...

Page 185: ...2 3 4 2 One DDR3 Device A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16 bit bank 7 7 2 3 4 2 1 CK and ADDR_CTRL Topologies One DDR3 Device Figure 7 58 shows the topology of the CK net classes and Figure 7 59 shows the topology for the corresponding ADDR_CTRL net classes Figure 7 58 CK Topology for One DDR3 Device Figure 7 59 ADDR_CTRL To...

Page 186: ...Routing for One DDR3 Device 7 7 2 3 5 Data Topologies and Routing Definition No matter the number of DDR3 devices used the data line topology is always point to point so its definition is simple 7 7 2 3 5 1 DQS x and DQ x Topologies Any Number of Allowed DDR3 Devices DQS x lines are point to point differential and DQ x lines are point to point singled ended Figure 7 62 and Figure 7 63 show these t...

Page 187: ...logy x 0 1 Figure 7 63 DQ x Topology 7 7 2 3 5 2 DQS x and DQ x Routing Any Number of Allowed DDR3 Devices Figure 7 64 and Figure 7 65 show the DQS x and DQ x routing x 0 1 Figure 7 64 DQS x Routing With Any Number of Allowed DDR3 Devices x 0 1 Figure 7 65 DQ x Routing With Any Number of Allowed DDR3 Devices Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 187 ...

Page 188: ...or the address bus are determined CACLM is determined similarly for other address bus configurations that is it is based on the longest net of the CK and ADDR_CTRL net class For CK and ADDR_CTRL routing these specifications are contained in Table 7 66 A It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 A8 on the DDR3 memories CACLM is based on the l...

Page 189: ...finition see Section 7 7 2 3 6 1 and Figure 7 66 10 Center to center spacing is allowed to fall to minimum w for up to 1250 mils of routed length 11 Signals from one DQ net class should be considered other DDR3 traces to another DQ net class 12 CK spacing set to ensure proper differential impedance Differential impedance should be Zo x 2 where Zo is the single ended impedance defined in Table 7 60...

Page 190: ...he DQ0 and DQ1 signal net classes 2 External termination disallowed Data termination should use built in ODT functionality 3 DQLMn is the longest Manhattan distance of a byte For definition see Section 7 7 2 3 6 2 and Figure 7 67 4 DQLM0 is the longest Manhattan length for the DQ0 net class 5 DQLM1 is the longest Manhattan length for the DQ1 net class 6 Length matching is only done within a byte L...

Page 191: ...8 tw SDAH 4 7 1 3 µs conditions 9 tr SDA Rise time SDA 1000 300 ns 10 tr SCL Rise time SCL 1000 300 ns 11 tf SDA Fall time SDA 300 300 ns 12 tf SCL Fall time SCL 300 300 ns 13 tsu SCLH SDAH Setup time high before SDA high for STOP condition 4 0 6 µs 14 tw SP Pulse duration spike must be suppressed 0 50 0 50 ns 1 A fast mode I2 C bus device can be used in a standard mode I2 C bus system but the req...

Page 192: ... for a START and a 17 th SDAL SCLL 4 0 6 µs repeated START condition 18 tw SCLL Pulse duration SCL low 4 7 1 3 µs 19 tw SCLH Pulse duration SCL high 4 0 6 µs 20 tsu SDAV SCLH Setup time SDA valid before SCL high 250 100 ns 21 th SCLL SDAV Hold time SDA valid after SCL low 0 3 45 0 0 9 µs Pulse duration SDA high between STOP and START 22 tw SDAH 4 7 1 3 µs conditions 23 tr SDA Rise time SDA 1000 30...

Page 193: ...Input setup time TDI valid to TCK high 3 3 ns 3 tsu TMS TCKH Input setup time TMS valid to TCK high 3 3 ns th TCKH TDI Input hold time TDI valid from TCK high 8 05 8 05 ns 4 th TCKH TMS Input hold time TMS valid from TCK high 8 05 8 05 ns Table 7 72 Switching Characteristics for JTAG see Figure 7 70 OPP100 OPP50 NO PARAMETER UNIT MIN MAX MIN MAX 2 td TCKL TDO Delay time TCK low to TDO valid 3 27 6...

Page 194: ...OAD Output load capacitance pF Raster mode 3 30 7 10 1 LCD Interface Display Driver LIDD Mode Table 7 74 Timing Requirements for LCD LIDD Mode see Figure 7 72 through Figure 7 80 OPP100 NO UNIT MIN MAX Setup time LCD_DATA 15 0 valid before 16 tsu LCD_DATA LCD_MEMORY_CLK 18 ns LCD_MEMORY_CLK high Hold time LCD_DATA 15 0 valid after 17 th LCD_MEMORY_CLK LCD_DATA 0 ns LCD_MEMORY_CLK high 18 tt LCD_DA...

Page 195: ...h to 14 td LCD_MEMORY_CLK LCD_DATAZ 0 7 ns LCD_DATA 15 0 high Z Delay time LCD_MEMORY_CLK high to 15 td LCD_MEMORY_CLK LCD_DATA 0 7 ns LCD_DATA 15 0 driven 19 tt LCD_MEMORY_CLK Transition time LCD_MEMORY_CLK 1 2 5 ns 20 tt LCD_DATA Transition time LCD_DATA 1 10 ns A Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK The first LCD_MEMORY_CLK waveform is onl...

Page 196: ... shown as a reference of the internal clock that sequences the other signals The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in Hitachi mode Figure 7 72 Data Write in Hitachi Mode A Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK The first LCD_MEMORY_CLK waveform is only shown as a r...

Page 197: ...tions that do not require an external LCD_MEMORY_CLK The first LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals The second LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in Hitachi mode Figure 7 74 Data Read in Hitachi Mode Copyright 2011 2015 Texas Instruments Incorporated Perip...

Page 198: ... ti com A Motorola mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 75 Micro In...

Page 199: ... MAY 2015 A Motorola mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 76 Micro ...

Page 200: ...perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 77 Micro Interface Graphic Display Motorola Status 200 P...

Page 201: ...15 A Intel mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 78 Micro Interface ...

Page 202: ...ww ti com A Intel mode can be configured to perform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 79 Micro Int...

Page 203: ...erform asynchronous operations or synchronous operations When configured in asynchronous mode LCD_MEMORY_CLK is not required so it performs the CS1 function When configured in synchronous mode LCD_MEMORY_CLK performs the MCLK function LCD_MEMORY_CLK is also shown as a reference of the internal clock that sequences the other signals Figure 7 80 Micro Interface Graphic Display Intel Status Copyright...

Page 204: ...CLK Transition time LCD_PCLK 0 5 2 4 0 5 2 4 ns 13 tt LCD_DATA Transition time LCD_DATA 0 5 2 4 0 5 2 4 ns Frame to frame timing is derived through the following parameters in the LCD RASTER_TIMING_1 register Vertical front porch VFP Vertical sync pulse width VSW Vertical back porch VBP Lines per panel LPP_B10 LPP Line to line timing is derived through the following parameters in the LCD RASTER_TI...

Page 205: ... 1 to L 2 1 3 1 1 L 1 2 L 1 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 Figure 7 81 LCD Raster Mode Display Format Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 205 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 206: ...1 1 2 PPLMSB PPLLSB 16 1 to 2048 HBP 1 to 256 Line 1 1 to 256 HFP 1 to 64 HSW PPLMSB PPLLSB 16 1 to 2048 Line 2 LCD_AC_BIAS_EN ACTVID 11 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com Figure 7 82 LCD Raster Mode Active 206 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder L...

Page 207: ... LCD_AC_BIAS_EN ACB 0 to 255 ACB 0 to 255 1 4 P 4 1 3 P 3 1 2 P 2 1 L P L 1 6 P 6 1 2 P 2 1 1 P 1 1 L P L 1 to 256 11 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals Figure 7 83 LCD Raster Mode Passive Copyright 2011 2015 Texas Instruments...

Page 208: ...WS 1 1 2 3 4 5 PPLMSB PPLLSB 16 x 1 to 2048 7 9 11 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals Figure 7 84 LCD Raster Mode Control Signal Activation 208 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorpora...

Page 209: ... PPLMSB PPLLSB 16 x 1 to 2048 11 1 2 3 2 1 P 1 1 1 4 5 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 A The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals Figure 7 85 LCD Raster Mode Control Signal Deactivation Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Ti...

Page 210: ...DIF AES 3 IEC 60958 CP 430 transmission The receive section of the McASP peripheral supports the TDM synchronous serial format The McASP module can support one transmit data format either a TDM format or DIT format and one receive format at a time All transmit shift registers use the same format and all receive shift registers use the same format however the transmit and receive formats need not b...

Page 211: ...R and 4 6 ACLKX ext out ACLKR and 1 1 ACLKX int Hold time McASP x _AFSR and th ACLKRX McASP x _AFSX input valid after ACLKR and 6 0 4 0 4 ns AFSRX McASP x _ACLKR and ACLKX ext in McASP x _ACLKX ACLKR and 0 4 0 4 ACLKX ext out ACLKR and 11 5 15 5 ACLKX int Setup time McASP x _AXR input ACLKR and 7 tsu AXR ACLKRX valid before McASP x _ACLKR and 4 6 ns ACLKX ext in McASP x _ACLKX ACLKR and 4 6 ACLKX ...

Page 212: ...LKR X CLKRP CLKXP 1 B AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in B For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configur...

Page 213: ...utput valid with out Pad Loopback Delay time McASP x _ACLKX ACLKX int 0 6 0 6 transmit edge to McASP x _AXR ACLKX ext in 2 13 5 2 18 output valid 14 td ACLKX AXR ns Delay time McASP x _ACLKX ACLKX ext transmit edge to McASP x _AXR 2 13 5 2 18 out output valid with Pad Loopback Disable time McASP x _ACLKX ACLKX int 0 6 0 6 transmit edge to McASP x _AXR ACLKX ext in 2 13 5 2 18 output high impedance...

Page 214: ...A McASP x _ACLKR X CLKRP CLKXP 0 B AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com A For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in B For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver...

Page 215: ... valid before SPI_CLK 4 tsu SIMO SPICLK 12 92 12 92 ns active edge 2 3 Hold time SPI_D x SIMO valid after SPI_CLK 5 th SPICLK SIMO 12 92 12 92 ns active edge 2 3 Setup time SPI_CS valid before SPI_CLK first 8 tsu CS SPICLK 12 92 12 92 ns edge 2 9 th SPICLK CS Hold time SPI_CS valid after SPI_CLK last edge 2 12 92 12 92 ns 1 P SPI_CLK period 2 This timing applies to all configurations regardless of...

Page 216: ...n 2 Bit n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 3 2 1 2 3 1 4 5 4 5 5 4 9 1 9 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com Figure 7 88 SPI Slave Mode Receive Timing 216 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 217: ... n 2 Bit n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 3 6 6 2 1 2 3 1 6 6 9 6 9 3 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 www ti com SPRS717H OCTOBER 2011 REVISED MAY 2015 Figure 7 89 SPI Slave Mode Transmit Timing Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 217 Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 ...

Page 218: ... 1 1 04 1 1 04 1 2 08 1 2 08 1 Typical pulse duration 0 5P 0 5P 0 5P 0 5P 0 5P 0 5P 0 5P 0 5P tw SPICLKH ns SPI_CLK high 1 04 1 1 04 1 2 08 1 2 08 1 1 04 1 1 04 1 2 08 1 2 08 1 3 tr SPICLK Rising time SPI_CLK 3 82 3 82 3 82 3 82 ns tf SPICLK Falling time SPI_CLK 3 44 3 44 3 44 3 44 ns Delay time SPI_CLK 6 td SPICLK SIMO active edge to SPI_D x 3 57 3 57 4 62 4 62 3 57 3 57 4 62 4 62 ns SIMO transit...

Page 219: ...CTOBER 2011 REVISED MAY 2015 4 Case P 20 8 ns A TCS 1 TSPICLKREF TCS is a bit field of MCSPI_CH i CONF register Case P 20 8 ns A TCS 0 5 Fratio TSPICLKREF TCS is a bit field of MCSPI_CH i CONF register Note P SPI_CLK clock period 5 B TCS 0 5 TSPICLKREF Fratio TCS is a bit field of MCSPI_CH i CONF register Fratio Even 2 Figure 7 90 SPI Master Mode Receive Timing Copyright 2011 2015 Texas Instrument...

Page 220: ...t n 1 Bit n 2 Bit n 3 Bit 1 Bit 0 PHA 1 EPOL 1 POL 0 POL 1 8 9 3 6 6 2 1 2 3 1 6 6 AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 SPRS717H OCTOBER 2011 REVISED MAY 2015 www ti com Figure 7 91 SPI Master Mode Transmit Timing 220 Peripheral Information and Timings Copyright 2011 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links AM3359 AM3358 AM3357 AM3356 AM3354 AM335...

Page 221: ... UNIT MIN TYP MAX MIN TYP MAX 1 tsu CMDV CLKH Setup time MMC_CMD valid before MMC_CLK rising clock edge 4 1 4 1 ns Industrial extended temperature MMC0 2 3 76 3 76 40 C to 125 C Hold time MMC_CMD valid after 2 th CLKH CMDV ns MMC0 3 76 2 52 MMC_CLK rising clock edge All other MMC1 3 76 3 03 temperature ranges MMC2 3 76 3 0 3 tsu DATV CLKH Setup time MMC_DATx valid before MMC_CLK rising clock edge ...

Page 222: ... 5 P 0 5 P 7 tw CLKH Pulse duration MMC_CLK high ns tr CLK 1 tr CLK 1 8 tr CLK Rise time all signals 10 to 90 2 2 2 2 ns 9 tf CLK Fall time all signals 10 to 90 2 2 2 2 ns 1 P MMC_CLK period Figure 7 93 MMC x _CLK Timing Table 7 89 Switching Characteristics for MMC x _CMD and MMC x _DAT 7 0 Standard Mode see Figure 7 94 OPP100 OPP50 NO PARAMETER UNIT MIN TYP MAX MIN TYP MAX Delay time MMC_CLK fall...

Page 223: ...NO PARAMETER UNIT MIN TYP MAX MIN TYP MAX td CLKL Delay time MMC_CLK rising clock edge to 12 3 14 3 17 5 ns CMD MMC_CMD transition Delay time MMC_CLK rising clock edge to 13 td CLKL DAT 3 14 3 17 5 ns MMC_DATx transition Figure 7 95 MMC x _CMD and MMC x _DAT 7 0 Output Timing High Speed Mode Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 223 Submit Documentat...

Page 224: ...ing Requirements Direct Input Mode see Figure 7 96 NO MIN MAX UNIT 1 tw GPI Pulse width GPI 2 P 1 ns 2 tr GPI Rise time GPI 1 00 3 00 ns tf GPI Fall time GPI 1 00 3 00 ns 3 tsk GPI Internal skew between GPI n 0 signals 2 PRU0 1 00 ns PRU1 3 00 1 P L3_CLK PRU ICSS ocp clock period 2 n 16 Figure 7 96 PRU ICSS PRU Direct Input Timing Table 7 93 PRU ICSS PRU Switching Requirements Direct Output Mode s...

Page 225: ...0 ns 7 th CLOCKIN DATAIN Hold time DATAIN valid after CLOCKIN 0 00 ns 8 tr DATAIN Rising time DATAIN 1 00 3 00 ns tf DATAIN Falling time DATAIN 1 00 3 00 ns Figure 7 98 PRU ICSS PRU Parallel Capture Timing Rising Edge Mode Figure 7 99 PRU ICSS PRU Parallel Capture Timing Falling Edge Mode 7 14 1 3 PRU ICSS PRU Shift Mode Electrical Data and Timing Table 7 95 PRU ICSS PRU Timing Requirements Shift ...

Page 226: ...t Out Timing 7 14 2 PRU ICSS EtherCAT PRU ICSS ECAT Table 7 97 PRU ICSS ECAT Timing Conditions PARAMETER MIN MAX UNIT Output Condition Cload Capacitive load for each bus line 30 pF 7 14 2 1 PRU ICSS ECAT Electrical Data and Timing Table 7 98 PRU ICSS ECAT Timing Requirements Input Validated with LATCH_IN see Figure 7 102 NO MIN MAX UNIT 1 tw EDIO_LATCH_IN Pulse width EDIO_LATCH_IN 100 00 ns 2 tr E...

Page 227: ...7 103 NO MIN MAX UNIT 1 tw EDC_SYNCx_OUT Pulse width EDC_SYNCx_OUT 100 00 ns 2 tr EDC_SYNCx_OUT Rising time EDC_SYNCx_OUT 1 00 3 00 ns 3 tf EDC_SYNCx_OUT Falling time EDC_SYNCx_OUT 1 00 3 00 ns 4 tsu EDIO_DATA_IN Setup time EDIO_DATA_IN valid before 20 00 ns EDC_SYNCx_OUT EDC_SYNCx_OUT active edge 5 th EDC_SYNCx_OUT Hold time EDIO_DATA_IN valid after EDC_SYNCx_OUT 20 00 ns EDIO_DATA_IN active edge...

Page 228: ...alid after EDIO_SOF active 20 00 ns edge 6 tr EDIO_DATA_IN Rising time EDIO_DATA_IN 1 00 3 00 ns tf EDIO_DATA_IN Falling time EDIO_DATA_IN 1 00 3 00 ns 1 P PRU ICSS IEP clock source period Figure 7 104 PRU ICSS ECAT Input Validated with SOF Table 7 101 PRU ICSS ECAT Timing Requirements LATCHx_IN see Figure 7 105 NO MIN MAX UNIT 1 tw EDC_LATCHx_IN Pulse duration EDC_LATCHx_IN 3 P 1 ns 2 tr EDC_LATC...

Page 229: ...ng Conditions PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1 1 3 1 ns tF Input signal fall time 1 1 3 1 ns Output Condition CLOAD Output load capacitance 3 20 pF 1 Except when specified otherwise 7 14 3 1 PRU ICSS MDIO Electrical Data and Timing Table 7 104 PRU ICSS MDIO Timing Requirements MDIO_DATA see Figure 7 106 NO MIN TYP MAX UNIT 1 tsu MDIO MDC Setup time MDIO valid...

Page 230: ...7 14 3 2 PRU ICSS MII_RT Electrical Data and Timing Table 7 107 PRU ICSS MII_RT Timing Requirements MII_RXCLK see Figure 7 109 10 Mbps 100 Mbps NO UNIT MIN TYP MAX MIN TYP MAX 1 tc RX_CLK Cycle time RX_CLK 399 96 400 04 39 996 40 004 ns 2 tw RX_CLKH Pulse duration RX_CLK high 140 260 14 26 ns 3 tw RX_CLKL Pulse duration RX_CLK low 140 260 14 26 ns 4 tt RX_CLK Transition time RX_CLK 3 3 ns Figure 7...

Page 231: ...TXCLK Timing Table 7 109 PRU ICSS MII_RT Timing Requirements MII_RXD 3 0 MII_RXDV and MII_RXER see Figure 7 111 10 Mbps 100 Mbps NO UNIT MIN TYP MAX MIN TYP MAX tsu RXD RX_CLK Setup time RXD 3 0 valid before RX_CLK 1 tsu RX_DV RX_CLK Setup time RX_DV valid before RX_CLK 8 8 ns tsu RX_ER RX_CLK Setup time RX_ER valid before RX_CLK th RX_CLK RXD Hold time RXD 3 0 valid after RX_CLK 2 th RX_CLK RX_DV...

Page 232: ...ceiver Transmitter PRU ICSS UART Table 7 111 Timing Requirements for PRU ICSS UART Receive see Figure 7 113 NO MIN MAX UNIT 3 tw RX Pulse duration receive start stop data bit 0 96U 1 1 05U 1 ns 1 U UART baud time 1 programmed baud rate Table 7 112 Switching Characteristics Over Recommended Operating Conditions for PRU ICSS UART Transmit see Figure 7 113 NO PARAMETER MIN MAX UNIT 1 ƒbaud baud Maxim...

Page 233: ...Requirements for UARTx Receive see Figure 7 114 NO MIN MAX UNIT 3 tw RX Pulse duration receive start stop data bit 0 96U 1 1 05U 1 ns 1 U UART baud time 1 programmed baud rate Table 7 114 Switching Characteristics for UARTx Transmit see Figure 7 114 NO PARAMETER MIN MAX UNIT 1 ƒbaud baud Maximum programmable baud rate 3 6864 MHz 2 tw TX Pulse duration transmit start stop data bit U 2 1 U 2 1 ns 1 ...

Page 234: ...RT IrDA receive and transmit modes Figure 7 115 UART IrDA Pulse Parameters Table 7 115 UART IrDA Signaling Rate and Pulse Duration Receive Mode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MIN MAX SIR 2 4 Kbps 1 41 88 55 µs 9 6 Kbps 1 41 22 13 µs 19 2 Kbps 1 41 11 07 µs 38 4 Kbps 1 41 5 96 µs 57 6 Kbps 1 41 4 34 µs 115 2 Kbps 1 41 2 23 µs MIR 0 576 Mbps 297 2 518 8 ns 1 152 Mbps 149 6 258 4 ns FI...

Page 235: ...ps 78 1 78 1 µs 9 6 Kbps 19 5 19 5 µs 19 2 Kbps 9 75 9 75 µs 38 4 Kbps 4 87 4 87 µs 57 6 Kbps 3 25 3 25 µs 115 2 Kbps 1 62 1 62 µs MIR 0 576 Mbps 414 419 ns 1 152 Mbps 206 211 ns FIR 4 Mbps single pulse 123 128 ns 4 Mbps double pulse 248 253 ns Copyright 2011 2015 Texas Instruments Incorporated Peripheral Information and Timings 235 Submit Documentation Feedback Product Folder Links AM3359 AM3358 ...

Page 236: ...nd accelerate development for smart appliance industrial and networking applications It is a low cost development platform based on the ARM Cortex A8 processor that is integrated with options such as Dual Gigabit Ethernet DDR3 and LCD touch screen AM3359 Industrial Communications Engine The AM3359 Industrial Communications Engine ICE is a development platform targeted for systems that specifically...

Page 237: ...upport tools have been characterized fully and the quality and reliability of the device have been demonstrated fully TI s standard warranty applies Predictions show that prototype devices X or P have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is u...

Page 238: ...he Cortex A8 core used on your device see the AM335x Sitara Processors Silicon Errata SPRZ360 Cortex A8 Technical Reference Manual This is the technical reference manual for the Cortex A8 processor A copy of this document can be obtained via the internet at http infocenter arm com or from your Texas Instruments representative ARM Core Cortex A8 AT400 AT401 Errata Notice Provides a list of advisori...

Page 239: ...rk of ARM Ltd or its subsidiaries ARM Cortex are registered trademarks of ARM Ltd or its subsidiaries EtherCAT is a registered trademark of EtherCAT Technology Group Android is a trademark of Google Inc PowerVR SGX is a trademark of Imagination Technologies Limited Linux is a registered trademark of Linus Torvalds All other trademarks are the property of their respective owners 8 6 Electrostatic D...

Page 240: ...mented on the ZCE package makes it possible to build an AM335x based product with a 4 layer PCB but a 4 layer PCB may not meet system performance goals Therefore system performance using a 4 layer PCB design must be evaluated during product design 9 2 Packaging Information The following pages include mechanical packaging and orderable information This information is the most current data available...

Page 241: ...b Br SNAGCU Level 3 260C 168 HR 40 to 105 AM3352BZCEA60 AM3352BZCED30 ACTIVE NFBGA ZCE 298 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3352BZCED30 AM3352BZCED60 ACTIVE NFBGA ZCE 298 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3352BZCED60 AM3352BZCZ100 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3352BZCZ100 AM3352BZCZ30 ACTIV...

Page 242: ...AM3354BZCED60 ACTIVE NFBGA ZCE 298 160 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3354BZCED60 AM3354BZCZ100 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3354BZCZ100 AM3354BZCZ30 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 0 to 90 AM3354BZCZ30 AM3354BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C...

Page 243: ...CTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3356BZCZD30 AM3356BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 90 AM3356BZCZD60 AM3357BZCZA30 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 105 AM3357BZCZA30 AM3357BZCZA60 ACTIVE NFBGA ZCZ 324 126 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 4...

Page 244: ...eadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak ...

Page 245: ...N ADDENDUM www ti com 21 May 2015 Addendum Page 5 OTHER QUALIFIED VERSIONS OF AM3358 Enhanced Product AM3358 EP NOTE Qualified Version Definitions Enhanced Product Supports Defense Aerospace and Medical Applications ...

Page 246: ......

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Page 248: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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