Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.9
Ethernet Media Access Controller and Switch Subsystem: C0_TX_PEND and
C0_RX_PEND Interrupts Not Connected to ARM Cortex-A8
Revisions Affected
1.0
Details
The Ethernet Media Access Controller/Switch (CPSW) subsystem C0_TX_PEND and
C0_RX_PEND interrupt outputs provide a single transmit interrupt that combines
transmit channel interrupts TXPEND[7:0] and a single receive interrupt that combines
receive channel interrupts RXPEND[7:0]. The TXPEND[0] and RXPEND[0] interrupt
outputs are connected to the ARM Cortex-A8 interrupt controller (INTC) rather than the
C0_TX_PEND and C0_RX_PEND interrupt outputs. This only allows channel 0 to
interrupt the ARM Cortex-A8.
The C0_TX_PEND and C0_RX_PEND interrupt outputs are the only interrupt outputs
that support interrupt pacing. If transmit channel interrupts 1-7, receive channel interrupts
1-7, or interrupt pacing is required, the following workaround must be implemented.
Workarounds
DMTIMER Workaround
The C0_TX_PEND and C0_RX_PEND interrupts can be re-routed to the ARM Cortex-A8
through two of the AM335x timers. TIMER5 and TIMER6 can be used when configured
to operate in capture mode. The time captured while operating in this mode is not
relevant, since the capture event notification to the ARM Cortex-A8 represents the
original causal interrupts coming from the EMAC and Switch subsystem.
The re-routed interrupts path are:
•
ARM Cortex-A8: TINT5 (interrupt 93) <-- TIMER5 Capture Event <-- [Event Capture
Mux: event 8] <-- EMAC and Switch: C0_RX_PEND
•
ARM Cortex-A8: TINT6 (interrupt 94) <-- TIMER6 Capture Event <-- [Event Capture
Mux: event 9] <-- EMAC and Switch: C0_TX_PEND
Configuration
The following configurations are required to use timer capture module interrupts:
•
TIMER5 and TIMER6 are enabled with capture mode during initialization.
–
Set bit 2 of the TIMER5 IRQENABLE set register located at 0x4804_602C to 1b.
–
Set bit 2 of the TIMER6 IRQENABLE set register located at 0x4804_802C to 1b.
•
Write the value 0x908 to the TIMER_EVT_CAPT register located at 0x44E1_0FD0 to
select EMAC and Switch event 8 (C0_RX_PEND) for TIMER 5 and EMAC and
Switch event 9 (C0_TX_PEND) for TIMER6.
•
Configure TIMER5 and TIMER6 to single-capture mode by resetting the
CAPT_MODE bit of each TCLR register.
–
Reset bit 13 of the TIMER5 TCLR register located at 0x4804_6038 to 0b.
–
Reset bit 13 of the TIMER6 TCLR register located at 0x4804_8038 to 0b.
•
Select rising-edge transition by setting the TCM bit of the TCLR register.
–
Set bit 8 of the TIMER5 TCLR register located at 0x4804_6038 to 1b.
–
Set bit 8 of the TIMER6 TCLR register located at 0x4804_8038 to 1b.
•
Use ARM Cortex-A8 interrupt 93 for C0_RX_PEND and interrupt 94 for
C0_TX_PEND instead of interrupts 41 and 42.
Interrupt Servicing
The following is the recommended procedure for servicing interrupts. This method clears
and re-enables the interrupts properly to ensure no interrupts are missed by the
DMTimer edge detection logic. This procedure applies for both receive and transmit
interrupts.
•
Clear the timer capture interrupt by writing 1 to the TCAR_IT_FLAG bit of the
respective IRQSTATUS register.
15
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
