Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.24
Boot: System Boot is Not Reliable if Reset is Asserted While Operating in OPP50
Revisions Affected
2.1, 2.0, 1.0
Details
The system attempts to boot using the ARM (A8), L3, L4, and respective DDR clock
frequencies defined by OPP100 when a reset is asserted. The system may fail to boot if
the system is operating with reduced VDD_MPU and VDD_CORE power supply voltages
as defined by OPP50 when reset is asserted. This issue occurs because the device is
being operated at OPP100 clock frequencies with OPP50 supply voltages. This
unsupported operating condition potentially over-clocks the logic which was only timing
closed to operate at OPP50 clock frequencies with OPP50 supply voltages.
There are three basic reset sources, the PWRONRSTn terminal, the WARMRSTn
terminal, and the internal watchdog timer, that need to be considered when designing a
product that supports OPP50.
It is important to return VDD_MPU and VDD_CORE power supplies to OPP100 defined
voltages before any of these resets sources are asserted.
Workarounds
Only source the PWRONRSTn terminal from a power management circuit that always
returns VDD_MPU and VDD_CORE power supplies to OPP100 defined voltages before
asserting PWRONRSTn.
There are two possible workarounds that can be applied to the other two reset sources.
The first workaround provides the lowest power consumption option but eliminates the
watchdog timer and WARMRSTn terminal functions. The second workaround retains the
watchdog timer and WARMRSTn terminal functions, but causes the device to consume
higher power.
•
Disable the watchdog timer and do not assert the WARMRSTn terminal while the
VDD_MPU and VDD_CORE power supply voltages are less than those defined by
OPP100.
•
Retain the VDD_MPU and VDD_CORE power supply voltages defined by OPP100
while operating the ARM (A8), L3, L4, and the respective DDR clocks at the reduced
frequencies defined by OPP50.
26
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
