Usage Notes and Known Design Exceptions to Functional Specifications
Where:
–
Rseries_max is the maximum value of the series resistor
–
ADC_ClkDiv is the decimal value of the ADC_CLKDIV register bits [15:0]
–
SampleDelay is the decimal value of the respective STEPDELAY register bits [31:24]
–
CLK_M_OSC is the frequency of the reference clock connected to OSC0
–
Rsource_max is the maximum output impedance of the source.
In the example above, if we assume ADC_ClkDiv is configured to 7 with
SampleDelay configured to 0 and a 24-MHz reference clock, Rseries_max would be
5547
Ω
minus Rsource_max. Assuming Rsource_max is 47
Ω
, the series resistor
inserted on the analog input signal should be less than 5500
Ω
to provide an
accurate voltage measurement.
Note: If a higher value of Rseries_max is required, it may be necessary to increase
the sample time by increasing SampleDelay to provide more time for the input
capacitance to charge.
•
TSC_ADC AIN terminals not used:
The preferred option is to have each unused AIN terminal connected to VSSA_ADC
through a 500-
Ω
resistor. Another option would be to leave the unused AIN terminals
open-circuit without any PCB traces connected to these terminals.
•
TSC_ADC VREFP terminal connected to VDDA_ADC and VREFN terminal
connected VSSA_ADC:
No action required for the VREFP and VREFN terminals.
•
TSC_ADC VREFP terminal not connected to VDDA_ADC and VREFN terminal
not connected to VSSA_ADC:
Insert a series resistor on each VREFP and VREFN terminal with a 0.1-uF
decoupling capacitor connected directly to each VREFP and VREFN terminal. The
series resistor value should be selected to limit output current to an acceptable level
for the VREFP and VREFN sources during this temporary period when VDD_CORE
is not applied during power-up.
The effect on ADC performance also needs to be considered when selecting the
series resistor value. The combined resistance of the series resistor and maximum
output impedance of each VREFP and VREFN source should be less than 100
Ω
to
minimize reduction in ADC performance. This low source impedance requirement
may cause the VREFP and VREFN sources to source or sink several mA of current
during this temporary period. For example: If the combined minimum resistance of
the series resistor and output impedance of the source is 50
Ω
, the worst case
current requirement during this temporary period would be [1.89 V (maximum supply
voltage) / 50
Ω
] = 37.8 mA while the typical current requirement for these sources
during normal operation would be about 90 uA.
35
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
