4 Functional Block Diagram
CC2652RB
General Hardware Peripherals and Modules
Main CPU
Up to
352KB
Flash
with 8KB
Cache
Sensor Interface
cJTAG
Up to
80KB
SRAM
256KB
ROM
Arm
®
Cortex
®
-M4F
Processor
BAW, LDO, Clocks, and References
Optional DC/DC Converter
RF Core
Arm
®
Cortex
®
-M0
Processor
DSP Modem
16KB
SRAM
ROM
ULP Sensor Controller
Low-Power Comparator
12-bit ADC, 200 ks/s
Constant Current Source
SPI-I
2
C Digital Sensor IF
4KB SRAM
Time-to-Digital Converter
4× 32-bit Timers
2× SSI (SPI)
Watchdog Timer
Temperature and
Battery Monitor
RTC
I
2
C and I
2
S
2× UART
32 ch. µDMA
31 GPIOs
AES-256, SHA2-512
ECC, RSA
ADC
ADC
Digital PLL
48 MHz
69 µA/MHz
2.4 GHz
TRNG
Figure 4-1. CC2652RB Block Diagram
SWRS232D – FEBRUARY 2019 – REVISED FEBRUARY 2021
4
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