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7.2 Signal Descriptions – RGZ Package

Table 7-1. Signal Descriptions – RGZ Package

PIN

I/O

TYPE

DESCRIPTION

NAME

NO.

DCDC_SW

—

Power

Output from internal DC/DC converter. Tie to ground for external
regulator mode (1.7-V to 1.95-V operation).

(1)

DCOUPL

—

Power

For decoupling of internal 1.27 V regulated digital-supply

(2)

DIO_0

I/O

Digital

GPIO

DIO_1

I/O

Digital

GPIO

DIO_2

I/O

Digital

GPIO

DIO_3

I/O

Digital

GPIO

DIO_4

I/O

Digital

GPIO

DIO_5

I/O

Digital

GPIO, high-drive capability

DIO_6

I/O

Digital

GPIO, high-drive capability

DIO_7

I/O

Digital

GPIO, high-drive capability

DIO_8

I/O

Digital

GPIO

DIO_9

I/O

Digital

GPIO

DIO_10

I/O

Digital

GPIO

DIO_11

I/O

Digital

GPIO

DIO_12

I/O

Digital

GPIO

DIO_13

I/O

Digital

GPIO

DIO_14

I/O

Digital

GPIO

DIO_15

I/O

Digital

GPIO

DIO_16

I/O

Digital

GPIO, JTAG_TDO, high-drive capability

DIO_17

I/O

Digital

GPIO, JTAG_TDI, high-drive capability

DIO_18

I/O

Digital

GPIO

DIO_19

I/O

Digital

GPIO

DIO_20

I/O

Digital

GPIO

DIO_21

I/O

Digital

GPIO

DIO_22

I/O

Digital

GPIO

DIO_23

I/O

Digital or Analog

GPIO, analog capability

DIO_24

I/O

Digital or Analog

GPIO, analog capability

DIO_25

I/O

Digital or Analog

GPIO, analog capability

DIO_26

I/O

Digital or Analog

GPIO, analog capability

DIO_27

I/O

Digital or Analog

GPIO, analog capability

DIO_28

I/O

Digital or Analog

GPIO, analog capability

DIO_29

I/O

Digital or Analog

GPIO, analog capability

DIO_30

I/O

Digital or Analog

GPIO, analog capability

EGP

—

GND

Ground – exposed ground pad

(3)

JTAG_TMSC

I/O

Digital

JTAG TMSC, high-drive capability

JTAG_TCKC

Digital

JTAG TCKC

RESET_N

Digital

Reset, active low. No internal pullup resistor

RF_P

—

Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX

RF_N

—

Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX

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CC2652RB

SWRS232D – FEBRUARY 2019 – REVISED FEBRUARY 2021

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CC2652RB

Summary of Contents for SimpleLink CC2652RB

Page 1: ...e supply voltage range Normal operation 1 8 to 3 8 V External regulator mode 1 7 to 1 95 V Active mode RX 7 3 mA Active mode TX 0 dBm 7 9 mA Active mode TX 5 dBm 10 2 mA Active mode MCU 48 MHz CoreMar...

Page 2: ...tocol operation through the Dynamic Multiprotocol Manager DMM software driver Integrated BAW resonator technology eliminates the need for external crystals without compromising latency or frequency st...

Page 3: ...w power RF transceiver capability to support multiple physical layers and RF standards The CC2652RB device is part of the SimpleLink MCU platform which consists of Wi Fi Bluetooth Low Energy Thread Zi...

Page 4: ...er Low Power Comparator 12 bit ADC 200 ks s Constant Current Source SPI I2 C Digital Sensor IF 4KB SRAM Time to Digital Converter 4 32 bit Timers 2 SSI SPI Watchdog Timer Temperature and Battery Monit...

Page 5: ...d IEEE 802 15 4 2006 2 4 GHz OQPSK DSSS1 8 250 kbps RX 19 8 14 Timing and Switching Characteristics 19 8 15 Peripheral Characteristics 25 8 16 Typical Characteristics 33 9 Detailed Description 49 9 1...

Page 6: ...wire 2 wire and 1 wire PTA coexistence mechanisms to the Radio Section list in Section 1 Features 1 Added Wireless protocols to Section 1 1 Changed the frequency of the input tone for 14 bit and 15 b...

Page 7: ...48 CC2652RB Multiprotocol Bluetooth 5 2 Low Energy Zigbee Thread 2 4 GHz proprietary FSK based formats 352 80 31 RGZ 7 mm 7 mm VQFN48 CC2652P Multiprotocol Bluetooth 5 2 Low Energy Zigbee Thread 2 4 G...

Page 8: ...DIO_25 DIO_24 VDDR VDDR_RF DIO_26 X48M_P X48M_N DIO_28 DIO_29 DIO_30 DIO_27 VDDS Figure 7 1 RGZ 7 mm 7 mm Pinout 0 5 mm Pitch Top View The following I O pins marked in Figure 7 1 in bold have high dri...

Page 9: ...8 I O Digital GPIO DIO_19 29 I O Digital GPIO DIO_20 30 I O Digital GPIO DIO_21 31 I O Digital GPIO DIO_22 32 I O Digital GPIO DIO_23 36 I O Digital or Analog GPIO analog capability DIO_24 37 I O Digi...

Page 10: ...the only ground connection for the device Good electrical connection to device ground on printed circuit board PCB is imperative for proper device operation 4 If internal DC DC converter is not used t...

Page 11: ...4 Including analog capable DIOs 5 VDDR VDDS VDDS2 and VDDS3 must be at the same potential 8 2 ESD Ratings VALUE UNIT VESD Electrostatic discharge Human body model HBM per ANSI ESDA JEDEC JS 001 1 All...

Page 12: ...l register retention RCOSC_LF 0 94 A RTC running CPU 80KB RAM and partial register retention XOSC_LF 1 09 A Standby with cache retention RTC running CPU 80KB RAM and partial register retention RCOSC_L...

Page 13: ...Operations Flash retention 105 C 11 4 Years at 105 C Flash sector erase current Average delta current 10 7 mA Flash sector erase time 4 Zero cycles 10 ms Flash write current Average delta current 4 by...

Page 14: ...uency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency 300 300 kHz Data rate error tolerance Difference between incoming data rate and t...

Page 15: ...ternally generated data rate 255 byte packets 175 175 ppm Co channel rejection 1 Wanted signal at 72 dBm modulated interferer in channel BER 10 3 3 5 dB Selectivity 1 MHz 1 Wanted signal at 72 dBm mod...

Page 16: ...10 3 measured at input level 70 dBm 36 45 2 dB Selectivity 5 MHz or more 1 Wanted signal at 67 dBm modulated interferer at 5 MHz BER 10 3 measured at input level 70 dBm 40 dB Selectivity image freque...

Page 17: ...at 67 dBm modulated interferer at 2 MHz from image frequency BER 10 3 measured at input level 70 dBm 7 36 2 dB Out of band blocking 3 30 MHz to 2000 MHz 16 dBm Out of band blocking 2003 MHz to 2399 M...

Page 18: ...l measurements are performed at the antenna input with a combined RX and TX path All measurements are performed conducted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Max output power...

Page 19: ...and desensitization 5 MHz from lower band edge Wanted signal at 97 dBm 3 dB above the sensitivity level CW jammer PER 1 60 dB Blocking and desensitization 10 MHz from lower band edge Wanted signal at...

Page 20: ...andby to Active 160 s MCU Active to Standby 36 s MCU Idle to Active 14 s 1 The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device and thus how long the device has...

Page 21: ...CL Crystal load capacitance 4 5 7 3 9 pF Start up time 2 200 s 1 Probing or otherwise stopping the crystal while the DC DC converter is enabled may cause permanent damage to the device 2 Start up tim...

Page 22: ...F Measured on a Texas Instruments reference design with Tc 25 C VDDS 3 0 V unless otherwise noted MIN TYP MAX UNIT Calibrated frequency 32 8 1 kHz Temperature coefficient 50 ppm C 1 When using RCOSC_L...

Page 23: ...s Figure 8 1 Figure 8 2 and Figure 8 3 2 When using the TI provided Power driver the SSI system clock is always 48 MHz SSIClk SSIFss SSITx SSIRx MSB LSB S2 S3 S1 4 to 16 bits Figure 8 1 SSI Timing for...

Page 24: ...With SPH 1 8 14 5 UART 8 14 5 1 UART Characteristics over operating free air temperature range unless otherwise noted PARAMETER MIN TYP MAX UNIT UART rate 3 MBaud CC2652RB SWRS232D FEBRUARY 2019 REVI...

Page 25: ...voltage scaling disabled 15 bit mode 200 kSamples s 150 Hz input tone 5 11 6 THD Total harmonic distortion Internal 4 3 V equivalent reference 2 200 kSamples s 9 6 kHz input tone 65 dB VDDS as refere...

Page 26: ...the gain offset compensation factors stored in FCFG1 This value is derived from the scaled value 4 3 V as follows Vref 4 3 V 1408 4095 1 48 V Reference voltage VDDS as reference input voltage scaling...

Page 27: ...3 0 V DAC charge pump OFF 53 2 VDDS 2 0 V DAC charge pump ON 48 7 VDDS 2 0 V DAC charge pump OFF 70 2 VDDS 1 8 V DAC charge pump ON 46 3 VDDS 1 8 V DAC charge pump OFF 88 9 Internal Load Continuous T...

Page 28: ...COUPL pre charge OFF code 1 0 01 VREF DCOUPL pre charge OFF code 255 1 21 VREF DCOUPL pre charge ON code 1 1 27 VREF DCOUPL pre charge ON code 255 2 46 VREF ADCREF code 1 0 01 VREF ADCREF code 255 1 4...

Page 29: ...or VREF VDDS 3 8 V code 1 0 03 V VREF VDDS 3 8 V code 255 3 61 VREF VDDS 3 0 V code 1 0 02 VREF VDDS 3 0 V code 255 2 85 VREF VDDS 1 8 V code 1 0 02 VREF VDDS 1 8 V code 255 1 71 VREF DCOUPL pre charg...

Page 30: ...nsor is automatically compensated for VDDS variation when using the TI provided driver 8 15 3 2 Battery Monitor Measured on a Texas Instruments reference design with Tc 25 C unless otherwise noted PAR...

Page 31: ...Time Comparator Tc 25 C VDDS 3 0 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 1 0 VDDS V Offset Measured at VDDS 2 5 mV Decision time Step from 10 mV to 10 m...

Page 32: ...at 8 mA load IOCURR 2 high drive GPIOs only 2 59 V GPIO VOL at 8 mA load IOCURR 2 high drive GPIOs only 0 42 V GPIO VOH at 4 mA load IOCURR 1 2 63 V GPIO VOL at 4 mA load IOCURR 1 0 40 V TA 25 C VDDS...

Page 33: ...COSC 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 2 5 3 3 5 4 4 5 5 5 5 6 D001 Figure 8 4 Active Mode MCU Current vs Supply Voltage VDDS Temperature C Current A Standby Current vs Temperature 80 kB RAM Ret...

Page 34: ...kHz XOSC VDDS 3 6 V 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 Figure 8 6 Standby Mode MCU Current vs Temperature VDDS 3 6 V CC2652RB SWRS232D FEBRUARY 2019 REVISED FEBRUARY 2021 www...

Page 35: ...Current vs Temperature BLE 1 Mbps 2 44 GHz Voltage V Current mA RX Current vs VDDS BLE 1 Mbps 2 44 GHz 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 5 5 6 6 5 7 7 5 8 8 5 9 9 5 10 10 5 11 11 5 12 Figure 8 8...

Page 36: ...TX Current vs Temperature BLE 1 Mbps 2 44 GHz Voltage V Current mA TX Current vs VDDS BLE 1 Mbps 2 44 GHz 0 dBm 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 6 6 5 7 7 5 8 8 5 9 9 5 10 10 5 11 11 5 12 12 5...

Page 37: ...g SmartRF Studio Typical Output Power dBm Typical Current Consumption mA 0x7217 5 5 3 10 1 0x4E63 4 4 2 9 5 0x385D 3 3 1 9 0x3259 2 2 1 8 5 0x2856 1 1 2 8 2 0x2853 0 0 1 7 8 0x12D6 5 5 0 6 7 0x0ACF 10...

Page 38: ...GHz Frequency GHz Sensitivity dBm Sensitivity vs Frequency IEEE 802 15 4 OQPSK DSSS1 8 250 kbps 2 4 2 408 2 416 2 424 2 432 2 44 2 448 2 456 2 464 2 472 2 48 105 104 103 102 101 100 99 98 97 96 95 Fig...

Page 39: ...ture C Sensitivity dBm Sensitivity vs Temperature IEEE 802 15 4 OQPSK DSSS1 8 250 kbps 2 44 GHz 40 30 20 10 0 10 20 30 40 50 60 70 80 85 105 104 103 102 101 100 99 98 97 96 95 Figure 8 14 Sensitivity...

Page 40: ...44 GHz Voltage V Sensitivity dBm Sensitivity vs VDDS BLE 1 Mbps 2 44 GHz DCDC Off 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 102 101 100 99 98 97 96 95 94 93 92 Figure 8 16 Sensitivity vs Supply Voltage...

Page 41: ...8 3 3 2 3 4 3 6 3 8 105 104 103 102 101 100 99 98 97 96 95 Figure 8 17 Sensitivity vs Supply Voltage VDDS IEEE 802 15 4 OQPSK DSSS1 8 250 kbps www ti com CC2652RB SWRS232D FEBRUARY 2019 REVISED FEBRUA...

Page 42: ...BLE 1 Mbps 2 44 GHz 0 dBm Temperature C Output Power dBm Output Power vs Temperature BLE 1 Mbps 2 44 GHz 5 dBm 40 30 20 10 0 10 20 30 40 50 60 70 80 85 3 3 2 3 4 3 6 3 8 4 4 2 4 4 4 6 4 8 5 5 2 5 4 5...

Page 43: ...2 44 GHz 0 dBm Voltage V Output Power dBm Output power vs VDDS BLE 1 Mbps 2 44 GHz 5 dBm 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 3 3 2 3 4 3 6 3 8 4 4 2 4 4 4 6 4 8 5 5 2 5 4 5 6 5 8 6 6 2 6 4 6 6 6...

Page 44: ...2 44 GHz 0 dBm Frequency GHz Output Power dBm Output Power vs Frequency BLE 1 Mbps 2 44 GHz 5 dBm 2 4 2 408 2 416 2 424 2 432 2 44 2 448 2 456 2 464 2 472 2 48 3 3 2 3 4 3 6 3 8 4 4 2 4 4 4 6 4 8 5 5...

Page 45: ...0 30 20 10 0 10 20 30 40 50 60 70 80 85 25 20 15 10 5 0 5 10 15 20 25 Figure 8 24 Compensated Frequency Accuracy vs Temperature 2 44 GHz www ti com CC2652RB SWRS232D FEBRUARY 2019 REVISED FEBRUARY 202...

Page 46: ...Figure 8 25 ENOB vs Input Frequency Frequency kHz ENOB Bit ENOB vs Sampling Frequency Vin 3 0 V Sine wave Internal reference Fin Fs 10 1 2 3 4 5 6 7 8 10 20 30 40 50 70 100 200 9 8 9 85 9 9 9 95 10 1...

Page 47: ...INL vs ADC Code ADC Code DNL LSB DNL vs ADC Code Vin 3 0 V Sine wave Internal reference 200 kSamples s 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 0 5 0 0 5 1 1 5 2 2 5 D065 Figure 8 28 DNL vs A...

Page 48: ...racy vs Temperature Voltage V Voltage V ADC Accuracy vs VDDS Vin 1 V Internal reference 200 kSamples s 1 8 2 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 1 1 001 1 002 1 003 1 004 1 005 1 006 1 007 1 008 1 009 1...

Page 49: ...itical applications Single cycle multiply instruction and hardware divide Hardware division and fast digital signal processing oriented multiply accumulate Saturating arithmetic for signal processing...

Page 50: ...memory usage and more space available for applications The new high speed mode allows data transfers up to 2 Mbps twice the speed of Bluetooth 4 2 and five times the speed of Bluetooth 4 0 without in...

Page 51: ...handling of digital sensors Dynamic reuse of hardware resources 40 bit accumulator supporting multiplication addition and shift Observability and debugging options Sensor Controller Studio is used to...

Page 52: ...rting mathematical operations needed for elliptic curves up to 512 bits and RSA key pair generation up to 1024 bits Through use of these modules and the TI provided cryptography drivers the following...

Page 53: ...clock or on each edge of a selected tick source Both one shot and periodical timer modes are available AUX Timer 2 is a 16 bit timer that can operate at 24 MHz 2 MHz or 32 kHz independent of the Sens...

Page 54: ...lable in the CC2652RB device The battery and temperature monitor allows an application to continuously monitor on chip temperature and supply voltage and respond to changes in environmental conditions...

Page 55: ...operation of the processor and all of the peripherals that are currently enabled The system clock can be any available clock source see Table 9 1 In Idle mode all active peripherals can be clocked bu...

Page 56: ...he BAW oscillator clock frequency is actively compensated by the modem internal firmware to ensure frequency stability over temperature voltage and device lifetime Every time the PLL is tuned wakeup o...

Page 57: ...the Integrated Passive Component section in CC13xx CC26xx Hardware Configuration and PCB Design Considerations for further information CC26x2RBEM 7ID Design Files The CC26x2RBEM 7ID reference design p...

Page 58: ...ore The built in EnergyTrace software is an energy based code analysis tool that measures and displays the application s energy profile and helps to optimize it for ultra low power consumption See Tab...

Page 59: ...es is now supported with CCS Cloud IAR Embedded Workbench for Arm IAR Embedded Workbench is a set of development tools for building and debugging embedded system applications using assembler C and C I...

Page 60: ...ons Invest once in the SimpleLink software development kit and use throughout your entire portfolio Learn more on ti com simplelink 11 2 Documentation Support To receive notification of documentation...

Page 61: ...Zigbee Alliance Inc Wi Fi is a registered trademark of Wi Fi Alliance Eclipse is a registered trademark of Eclipse Foundation IAR Embedded Workbench is a registered trademark of IAR Systems AB Window...

Page 62: ...st current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand na...

Page 63: ...retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature...

Page 64: ...e Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant CC2652RB1FRGZR VQFN RGZ 48 2500 330 0 16 4 7 3 7 3 1 1 12 0 16 0 Q2 PACKAGE MATERIA...

Page 65: ...ons are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm CC2652RB1FRGZR VQFN RGZ 48 2500 336 6 336 6 31 8 PACKAGE MATERIALS INFORMATION www ti com 3 Sep 2020 Pack Mate...

Page 66: ...IEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RGZ 48 PLASTIC QUADFLAT PACK NO LEAD 7...

Page 67: ...l thermal and mechanical performance PACKAGE OUTLINE 4219044 C 09 2020 www ti com VQFN 1 mm max height PLASTIC QUADFLAT PACK NO LEAD RGZ0048A A 0 08 C 0 1 C A B 0 05 C B SYMM SYMM PIN 1 INDEX AREA 7 1...

Page 68: ...ias under paste be filled plugged or tented EXAMPLE BOARD LAYOUT 4219044 C 09 2020 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE 15X 5 15...

Page 69: ...sign recommendations EXAMPLE STENCIL DESIGN 4219044 C 09 2020 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 67...

Page 70: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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