Public Version
PRCM Register Manual
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Bits
Field Name
Description
Type
Reset
5:3
CLKOUT2_DIV
This field controls the external output clock division;
RW
0x0
Other enums: Reserved
0x0: sys_clkout2 / 1
0x1: sys_clkout2 / 2
0x2: sys_clkout2 / 4
0x3: sys_clkout2 / 8
0x4: sys_clkout2 / 16
2
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0
1:0
CLKOUT2SOURCE
This field selects the external output clock source
RW
0x3
0x0: source is CORE_CLK
0x1: source is CM_SYS_CLK
0x2: source is CM_96M_FCLK
0x3: source is 54 MHz clock
Table 3-210. Register Call Summary for Register CM_CLKOUT_CTRL
PRCM Functional Description
•
:
PRCM Register Manual
•
Clock_Control_Reg_CM Register Summary
:
3.8.1.9
DSS_CM Registers
3.8.1.9.1 DSS_CM Register Summary
Table 3-211. DSS_CM Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
Reset Type
(Bits)
RW
32
0x0000 0000
0x4800 4E00
W
RW
32
0x0000 0010
0x4800 4E10
W
R
32
0x0000 0020
0x4800 4E20
C
RW
32
0x0000 0030
0x4800 4E30
W
RW
32
0x0000 0040
0x4800 4E40
W
RW
32
0x0000 0044
0x4800 4E44
W
RW
32
0x0000 0048
0x4800 4E48
W
R
32
0x0000 004C
0x4800 4E4C
C
3.8.1.9.2 DSS_CM Registers
Table 3-212. CM_FCLKEN_DSS
Address Offset
0x0000 0000
Physical Address
0x4800 4E00
Instance
DSS_CM
Description
Controls the modules functional clock activity.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EN_TV
EN_DSS2
EN_DSS1
510
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated