Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 511 / 3738

Public Version
www.ti.com
PRCM Register Manual
Bits Field Name Description Type Reset
31:3 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
2 EN_TV DSS_TV_FCLK functional clock control RW 0x0
0x0: DSS_TV_FCLK is disabled
0x1: DSS_TV_FCLK is enabled
1 EN_DSS2 Display Sub-System functional clock 2 control RW 0x0
0x0: DSS2_ALWON_FCLK is disabled
0x1: DSS2_ALWON_FCLK is enabled
0 EN_DSS1 Display Sub-System functional clock 1 control RW 0x0
0x0: DSS1_ALWON_FCLK is disabled
0x1: DSS1_ALWON_FCLK is enabled
Table 3-213. Register Call Summary for Register CM_FCLKEN_DSS
PRCM Functional Description
• DSS Power Domain Clock Controls : [0] [1] [2]
PRCM Basic Programming Model
• CM_FCLKEN_ <domain_name> (Functional Clock Enable Register) : [3]
• CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) : [4]
PRCM Register Manual
• DSS_CM Register Summary : [5]
Table 3-214. CM_ICLKEN_DSS
Address Offset 0x0000 0010
Physical Address 0x4800 4E10 Instance DSS_CM
Description Controls the modules interface clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_DSS
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 EN_DSS Display sub-system interface clock control RW 0x0
0x0: DSS_L3_ICLK and DSS_L4_ICLK are disabled
0x1: DSS_L3_ICLK and DSS_L4_ICLK are enabled
Table 3-215. Register Call Summary for Register CM_ICLKEN_DSS
PRCM Functional Description
• DSS Power Domain Clock Controls : [0]
PRCM Basic Programming Model
• CM_ICLKEN_ <domain_name> (Interface Clock Enable Register) : [1]
PRCM Register Manual
• DSS_CM Register Summary : [2]
511 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated