Public Version
General-Purpose Memory Controller
www.ti.com
Table 10-78. Register Call Summary for Register GPMC_ECC_CONFIG
General-Purpose Memory Controller
•
Error correction code engine (ECC)
•
NAND Device Basic Programming Model
[2] [3] [4] [5] [6] [7] [8] [9]
•
•
:
Table 10-79. GPMC_ECC_CONTROL
Address Offset
0x0000 01F8
Physical Address
0x6E00 01F8
Instance
GPMC
Description
ECC control
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
ECCPOINTER
ECCCLEAR
Bits
Field Name
Description
Type
Reset
31:9
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x000000
8
ECCCLEAR
Clear all ECC result registers
RW
0x0
Reads returns 0
Write 0x1 to this field clear all ECC result registers
Write 0x0 is ignored
7:4
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0
3:0
ECCPOINTER
Selects ECC result register (Reads to this field give the dynamic
RW
0x0
position of the ECC pointer - Writes to this field select the ECC result
register where the first ECC computation will be stored); Other
enums: writing other values disables the ECC engine (ECCENABLE
bit of
set to 0)
0x0: Writing 0x0 disables the ECC engine (ECCENABLE bit of
set to 0)
0x1: ECC result register 1 selected
0x2: ECC result register 2 selected
0x3: ECC result register 3 selected
0x4: ECC result register 4 selected
0x5: ECC result register 5 selected
0x6: ECC result register 6 selected
0x7: ECC result register 7 selected
0x8: ECC result register 8 selected
0x9: ECC result register 9 selected
Table 10-80. Register Call Summary for Register GPMC_ECC_CONTROL
General-Purpose Memory Controller
•
NAND Device Basic Programming Model
•
2218
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated