Texas Instruments OMAP36 Series, Technical Reference Manual

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bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 508
Row 509
Row 510
Row 511
P1o P1e P1o P1e P1o P1e P1o P1e
P2o P2e P2o P2e
P4o P4e
P8e
P8o
P8e
P8o
P8e
P8o
P8e
P8o
P16e
P16o
P16e
P16o
P2048e
P2048o
512 Bytes input
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 0
Row 1
Row 2
Row 3
Row 508
Row 509
Row 510
Row 511
P1o P1e P1o P1e P1o P1e P1o P1e
P2o P2e P2o P2e
P4o P4e
P8e
P8o
P8e
P8o
P8e
P8o
P8e
P8o
P16e
P16o
P16e
P16o
P2048e
P2048o
512 Bytes input
gpmc-029
Public Version
www.ti.com
General-Purpose Memory Controller
Figure 10-29. ECC Computation for a 512-Byte Data Stream (Read or Write)
For a 2-Kbytes page, four 512-byte ECC calculations plus one for the spare area are required. Results are
stored in the
GPMC_ECCj_RESULT registers (j = 1 to 9).
10.1.5.14.3.1.4 ECC Comparison and Correction
To detect an error, the computed ECC result must be XORed with the parity value stored in the spare
area of the accessed page.
• If the result of this logical XOR is all 0s, no error is detected and the read data is correct.
• If every second bit in the parity result is a 1, one bit is corrupted and is located at bit address (P2048o,
P1024o, P512o, P256o, P128o, P64o, P32o, P16o, P8o, P4o, P2o, P1o). The software must correct
the corresponding bit.
• If only one bit in the parity result is 1, it is an ECC error and the read data is correct.
10.1.5.14.3.1.5 ECC Calculation Based on 8-Bit Word
The 8-bit based ECC computation is used for 8-bit wide NAND device interfacing.
The 8-bit based ECC computation can be used for 16-bit wide NAND device interfacing to get backward
compatibility on the error-handling strategy used with 8-bit wide NAND devices. In this case, the 16-bit
wide data read from or written to the NAND device is fragmented into 2 bytes. According to little-endian
access, the least significant bit (LSB) of the 16-bit wide data is ordered first in the byte stream used for
8-bit based ECC computation.
10.1.5.14.3.1.6 ECC Calculation Based on 16-Bit Word
ECC computation based on a 16-bit word is used for 16-bit wide NAND device interfacing. This ECC
computation is not supported when interfacing an 8-bit wide NAND device, and the
GPMC.
GPMC_ECC_CONFIG [7] ECC16B bit must be set to 0 when interfacing an 8-bit wide NAND
device.
The parity computation based on 16-bit words affects the row and column parity mapping. The main
difference is that the odd and even parity bits P8o and P8e are computed on rows for an 8-bit based ECC
while there are computed on columns for a 16-bit based ECC.
Figure 10-30 and Figure 10-31 show a 128
Word 16 ECC computation scheme and a 256 Word16 ECC computation scheme.
2167 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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