Texas Instruments OMAP36 Series, Technical Reference Manual

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General-Purpose Memory Controller
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Bits Field Name Description Type Reset
1 ECC2RESULTSIZE Selects ECC size for ECC 2 result register RW 0x0
0x0: ECCSIZE0 selected
0x1: ECCSIZE1 selected
0 ECC1RESULTSIZE Selects ECC size for ECC 1 result register RW 0x0
0x0: ECCSIZE0 selected
0x1: ECCSIZE1 selected
Table 10-82. Register Call Summary for Register GPMC_ECC_SIZE_CONFIG
General-Purpose Memory Controller
• NAND Device Basic Programming Model : [0] [1] [2] [3]
• GPMC Register Summary : [4]
Table 10-83. GPMC_ECCj_RESULT
Address Offset 0x0000 0200 + (0x0000 0004 * k) Index j= 1 to 9 and k = 0 to 8
Physical Address 0x6E00 0200 + (0x0000 0004 * Instance GPMC
k)
Description ECC result register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
P8o P4o P2o P1o P8e P4e P2e P1e
P64o P32o P16o P64e P32e P16e
P512o P256o P128o P512e P256e P128e
P2048o P1024o P2048e P1024e
Bits Field Name Description Type Reset
31:28 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
27 P2048o Odd row parity bit 2048, only used for ECC computed on 512 Bytes R 0x0
26 P1024o Odd row parity bit 1024 R 0x0
25 P512o Odd row parity bit 512 R 0x0
24 P256o Odd row parity bit 256 R 0x0
23 P128o Odd row parity bit 128 R 0x0
22 P64o Odd row parity bit 64 R 0x0
21 P32o Odd row parity bit 32 R 0x0
20 P16o Odd row parity bit 16 R 0x0
19 P8o Odd row parity bit 8 R 0x0
18 P4o Odd Column Parity bit 4 R 0x0
17 P2o Odd Column Parity bit 2 R 0x0
16 P1o Odd Column Parity bit 1 R 0x0
15:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
11 P2048e Even row parity bit 2048, only used for ECC computed on 512 Bytes R 0x0
10 P1024e Even row parity bit 1024 R 0x0
9 P512e Even row parity bit 512 R 0x0
8 P256e Even row parity bit 256 R 0x0
7 P128e Even row parity bit 128 R 0x0
6 P64e Even row parity bit 64 R 0x0
5 P32e Even row parity bit 32 R 0x0
4 P16e Even row parity bit 16 R 0x0
3 P8e Even row parity bit 8 R 0x0
2 P4e Even column parity bit 4 R 0x0
2220 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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