Texas Instruments OMAP36 Series, Technical Reference Manual

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General-Purpose Memory Controller
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The GPMC. GPMC_ECC_CONTROL [3:0] ECCPOINTER field must be set to the correct value to select
the ECC result register to be used first in the list for the incoming ECC computation process. The
ECCPointer can be read to determine which ECC register is used in the next ECC result storage for the
ongoing ECC computation. The GPMC.
GPMC_ECCj_RESULT register value (j = 1 to 9) can be
considered valid when ECCPOINTER equals j + 1. When GPMC. GPMC_ECCj_RESULT (where j = 9) is
updated, ECCPOINTER is frozen at 10, and ECC computing is stopped (ECCENABLE = 0).
The ECC accumulator must be reset before any ECC computation accumulation process. The
GPMC.
GPMC_ECC_CONTROL [8] ECCCLEAR bit must be set to 1 (nonpersistent bit) to clear the
accumulator and all ECC result registers.
For each ECC result (each GPMC. GPMC_ECCj_RESULT register, j = 1 to 9), the number of bytes or
Word16s used for ECC computing accumulation can be selected from between two programmable values.
The ECCjRESULTSIZE bits (j = 1 to 9) in the GPMC. GPMC_ECC_SIZE_CONFIG register select which
programmable size value (ECCSIZE0 or ECCSIZE1) must be used for this ECC result (stored in
GPMC.
GPMC_ECCj_RESULT ).
The ECCSIZE0 and ECCSIZE1 fields allow selection of the number of bytes or Word16s used for ECC
computation accumulation. Any even values from 2 to 512 are allowed.
Flexibility in the number of ECCs computed and the number of bytes or Word16s used in the successive
ECC computations enables different NAND page error-correction strategies. Usually based on 256 or 512
bytes and on 128 or 256 Word16, the number of ECC results required is a function of the NAND device
page size. Specific ECC accumulation size can be used when computing the ECC on the NAND spare
byte.
For example, with a 2-Kbyte data page 8-bit-wide NAND device, eight ECCs accumulated on 256 bytes
can be computed and added to one extra ECC computed on the 24 spare bytes area where the eight ECC
results used for comparison and correction with the computed data page ECC are stored. The GPMC then
provides nine GPMC.
GPMC_ECCj_RESULT registers (j= 1 to 9) to store the results. In this case,
ECCSIZE0 is set to 256, and ECCSIZE1 is set to 24; the ECC[1:8]RESULTSIZE bits are set to 0, and the
ECC9RESULTSIZE bit is set to 1.
10.1.5.14.3.1.2 ECC Enabling
The GPMC. GPMC_ECC_CONFIG [3:0] ECCCS field selects the allocated chip-select. The
GPMC. GPMC_ECC_CONFIG [0] ECCENABLE bit enables ECC computation on the next detected read or
write access to the selected chip-select.
The ECCPOINTER, ECCCLEAR, ECCSIZE, ECCjRESULTSIZE (where j = 1 to 9), ECC16B, and ECCCS
fields must not be changed or cleared while an ECC computation is in progress.
The ECC accumulator and ECC result register must not be changed or cleared while an ECC computation
is in progress.
Table 10-5 describes the ECC enable settings.
Table 10-5. ECC Enable Settings
Bit Field Register Value Comments
ECCCS GPMC_ECC_CONFIG 0 -7 Selects the chip-select where ECC is computed
ECC16B GPMC_ECC_CONFIG 0/1 Selects column number for ECC calculation
ECCCLEAR GPMC_ECC_CONTROL 0 -7 Clears all ECC result registers
ECCPOINTER GPMC_ECC_CONTROL 0 -7 A write to this bit field selects the ECC result register
where the first ECC computation is stored. Set to 1
by default.
ECCSIZE1 GPMC_ECC_SIZE_CONFIG 0x00 -0xFF Defines ECCSIZE1
ECCSIZE0 GPMC_ECC_SIZE_CONFIG 0x00 - 0xFF Defines ECCSIZE0
ECCjRESULTSIZE GPMC_ECC_SIZE_CONFIG 0/1 Selects the size of ECCn result register
(j from 1 to 9)
ECCENABLE GPMC_ECC_CONFIG 1 Enables the ECC computation
2164Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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