Texas Instruments OMAP36 Series, Technical Reference Manual

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General-Purpose Memory Controller
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10.1.7.3 GPMC Register Description
This section provides a description of GPMC registers.
NOTE: All GPMC registers are aligned to 32-bit address boundaries. All register file accesses,
except to GPMC_NAND_DATA_i register, are little endian. If the GPMC_NAND_DATA_i
register location is accessed, the endianness is access-dependent.
Table 10-29. GPMC_REVISION
Address Offset 0x0000 0000
Physical Address 0x6E00 0000 Instance GPMC
Description This register contains the IP revision code.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
Bits Field Name Description Type Reset
31:8 Reserved Reads return 0. R 0x000000
7:0 REV IP revision R See
(1)
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
(1)
TI internal data
Table 10-30. Register Call Summary for Register GPMC_REVISION
General-Purpose Memory Controller
• GPMC Register Summary : [0]
Table 10-31. GPMC_SYSCONFIG
Address Offset 0x0000 0010
Physical Address 0x6E00 0010 Instance GPMC
Description This register controls the various parameters of the Interconnect.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTOIDLE
IDLEMODE
RESERVED
SOFTRESET
Bits Field Name Description Type Reset
31:5 RESERVED Write 0s for future compatibility. Reads return 0s. RW 0x0000000
4:3 IDLEMODE 0x0: Force-idle. An idle request is acknowledged unconditionally RW 0x0
0x1: No-idle. An idle request is never acknowledged
0x2: Smart-idle. Acknowledgment to an idle request is given based
on the internal activity of the module
0x3: Do not use
2 RESERVED Write 0 for future compatibility Reads returns 0 RW 0x0
2196 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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