Public Version
General-Purpose Memory Controller
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Table 10-89. GPMC_BCH_RESULT2_i
Address Offset
0x0000 0248 + (0x0000 0010 * i)
Index
i = 0 to 7
Physical Address
0x6E00 0248 + (0x0000 0010 * i)
Instance
GPMC
Description
BCH ECC result (bits 64 to 95)
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BCH_RESULT_2
Bits
Field Name
Description
Type
Reset
31:0
BCH_RESULT_2
BCH ECC result (bits 64 to 95)
RW
0x00000000
Table 10-90. Register Call Summary for Register GPMC_BCH_RESULT2_i
General-Purpose Memory Controller
•
NAND Device Basic Programming Model
•
Table 10-91. GPMC_BCH_RESULT3_i
Address Offset
0x0000 024C + (0x0000 0010 * i)
Index
i = 0 to 7
Physical Address
0x6E00 024C + (0x0000 0010 * i)
Instance
GPMC
Description
BCH ECC result (bits 96 to 103)
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
BCH_RESULT_3
Bits
Field Name
Description
Type
Reset
31:8
RESERVED
Write 0s for future compatibility. Read returns 0s.
R
0x000000
7:0
BCH_RESULT_3
BCH ECC result (bits 96 to 103)
RW
0x00
Table 10-92. Register Call Summary for Register GPMC_BCH_RESULT3_i
General-Purpose Memory Controller
•
NAND Device Basic Programming Model
•
Table 10-93. GPMC_BCH_SWDATA
Address Offset
0x0000 02D0
Physical Address
0x6E00 02D0
Instance
GPMC
Description
This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash
interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
BCH_DATA
Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Write 0s for future compatibility. Read returns 0s.
R
0x0000
15:0
BCH_DATA
Data to be included in the BCH calculation.
RW
0x0000
Only bits 0 to 7 are taken into account if the calculator is configured to use 8
bits data (
[7] ECC16B = 0)
2222
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
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