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General-Purpose Memory Controller
•
When the calculated ECC is replaced by dummy accesses, it must be written to the cache in a
second, separate phase. The ECC module is disabled during that time.
•
NAND writes its cache line (page) to the array.
Typical page read sequence:
•
Sequential read of a page. ECC is calculated on-the-fly.
•
ECC module buffers status determines the presence of errors.
2. Accesses to several memories may be interleaved by the GPMC, but only one of those memories can
be a NAND using the BCH engine at a time; in other words, only one BCH calculation (for example, for
a single page) can be on-going at any time. Note also that the sequential nature of NAND accesses
guarantees that the data is always written / read out in the same order. BCH-relevant accesses are
selected by the GPMCs chip-select.
3. Each page may hold up to 4 Kbytes of data, spare bytes not included. This means up to 8 * 512-byte
BCH messages. Since all the data is written / read out first, followed by the BCH ECC, this means that
the BCH engine must be able to hold 8 104-bit remainders or syndromes (or smaller, 52-bit ones) at
the same time.
The BCH module has the capacity to store all remainders internally. After the page start, an internal
counter is used to detect the 512-byte sector boundaries. On those boundaries, the current remainder
is stored and the divider reset for the next calculation. At the end of the page, the BCH module
contains all remainders.
4. NAND access cycles hold 8 or 16 bits of data each (1 or 2 bytes); Each NAND cycle takes at least 4
cycles of the GPMCs internal clock. This means the NAND flash timing parameters must define a
RDCYCLETIME and a WRCYCLETIME of at least 4 clock cycles after optimization when using the
BCH calculator.
5. The spare area is assumed to be large enough to hold the BCH ECC, that is, to have at least a
message of 13 bytes available per 512-byte sector of data. The zone of unused spare area by the
ECC may or may not be protected by the same ECC scheme, by extending the BCH message beyond
512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of space to cover
some spares bytes).
10.1.5.14.3.2.2 Memory-Mapping of the BCH Codeword
BCH encoding considers a block of data to protect as a polynomial message M(x). In our standard case,
512 bytes of data (that is, 2
12
bits = 4096 bits) are seen as a polynomial of degree 2
12
- 1 = 4095, with
parameters ranging from M0 to M4095. For 512 bytes of data, 52 bits are required for 4-bit error
correction, and 104 bits are required for 8-bit error correction. The ECC is a remainder polynomial R(x) of
degree 103 (or 51, depending on the selected mode). The complete codeword C(x) is the concatenation of
M(x) and R(x) as shown in
.
Table 10-6. Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
Message M(x)
ECC R(x)
Bit number
M4095
...
M0
R103
...
R0
If the message is extended by the addition of spare bytes to be protected by the same ECC, the principle
is still valid. For example, a 3-byte extension of the message gives a polynomial message M(x) of degree
((512 + 3) * 8) - 1 = 4119, for a total of 3+13 = 16 spare bytes of spare, all protected as part of the same
codeword.
The message and the ECC bits are manipulated and mapped in the GPMC byte-oriented system. The
ECC bits are stored in
,
and
(where i = 0 to 7).
10.1.5.14.3.2.2.1 Memory-Mapping of the Data Message
The data message mapping shall follow the following rules:
•
Bit endianness within a byte is little-endian, that is, the bytes LS bit is also the lowest-degree
polynomial parameter: a byte b7-b0 (with b0 the LS bit) represents a segment of polynomial b7 * x
(7+i)
+
b6 * x
(6+i)
+ ... + b0 * x
i
2169
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
