Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
30 TA_TO_X16 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in TA_TO_COUNTER bit field
0x0: The number of DSI_FCLK clock cycles defined in
TA_TO_COUNTER is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
TA_TO_COUNTER is multiplied by 16x
29 TA_TO_X8 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in TA_TO_COUNTER bit field
0x0: The number of DSI_FCLK clock cycles defined in
TA_TO_COUNTER is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
TA_TO_COUNTER is multiplied by 8x
28:16 TA_TO_COUNTER Turn around counter. It indicates the number of DSI_FCLK clock RW 0x1FFF
cycles to wait for the change of the Direction PPI signal
according to the TurnRequest signal
The value is from 0 to 8191.
15 FORCE_TX_STOP_ Control of ForceTxStopMode signal RW 0x0
MODE_IO
0x0: De-assertion of ForceTxStopMode. The hardware reset the
bit at the end of the ForceTXStopMode assertion. The SW can
reset the bit to stop the assertion of the ForceTXStopMode
signal prior to the completion of the period.
0x1: Assertion of ForceTxStopMode
14 STOP_STATE_X16_IO Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in STOP_STATE_COUNTER_IO bit field
0x0: The number of DSI_FCLK clock cycles defined in
STOP_STATE _COUNTER_IO is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
STOP_STATE _COUNTER_IO is multiplied by 16x
13 STOP_STATE_X4_IO Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1
defined in STOP_STATE_COUNTER_IO bit field
0x0: The number of DSI_FCLK clock cycles defined in
STOP_STATE _COUNTER_IO is multiplied by 1x
0x1: The number of DSI_FCLK clock cycles defined in
STOP_STATE _COUNTER_IO is multiplied by 4x
12:0 STOP_STATE_ Stop state counter. It indicates the number of DSI_FCLK clock RW 0x1FFF
COUNTER_IO cycles to assert ForceTXStopMode signal. The value is from 0 to
8191.
Table 7-389. Register Call Summary for Register DSI_TIMING1
Display Subsystem Functional Description
• ForceTxStopMode FSM : [0] [1] [2] [3] [4]
• TurnRequest FSM : [5] [6] [7] [8] [9]
• LP RX Timer : [10]
Display Subsystem Basic Programming Model
• Video Mode Transfer : [11] [12]
• Command Mode Transfer Example 1 : [13] [14]
• Command Mode Transfer Example 2 : [15] [16]
Display Subsystem Use Cases and Tips
• Configure DSI Timing and Virtual Channels : [17]
• Drive Stop State : [18] [19]
• Configure DSI Protocol Engine : [20] [21] [22] [23]
• Drive Stop State : [24] [25]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [26]
1930Display Subsystem SWPU177N – December 2009 – Revised November 2010
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