Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.0
1
0
P3DIR.0
P3IN.0
D
EN
Module X IN
1
0
Module X OUT
P3OUT.0
1
0
DVSS
DVCC
P3REN.0
ADC10AE0.5
Pad Logic
INCHx = 5
To ADC 10
1
USCI Direction
Control
P3.0/UCB0STE/UCA0CLK/A5
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C – MARCH 2013 – REVISED SEPTEMBER 2014
www.ti.com
6.19.11 Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Table 6-25. Port P3 (P3.0) Pin Functions
CONTROL BITS OR SIGNALS
(1)
PIN NAME (P1.x)
x
y
FUNCTION
P3DIR.x
P3SEL.x
ADC10AE0.y
P3.0
(2)
(I/O)
I: 0; O: 1
0
0
P3.0/UCB0STE/
0
5
UCB0STE/UCA0CLK
(3) (4)
X
1
0
UCA0CLK/A5
A5
(5)
X
X
1
(1)
X = Don't care
(2)
Default after reset (PUC, POR)
(3)
The pin direction is controlled by the USCI module.
(4)
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5)
Setting the ADC10AE0.y bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
60
Detailed Description
Copyright © 2013–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430G2744 MSP430G2544 MSP430G2444
