Texas Instruments MSP430G2744DA Manual Download Page 10

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MSP430G2744, MSP430G2544, MSP430G2444

SLAS892C – MARCH 2013 – REVISED SEPTEMBER 2014

www.ti.com

4.2

Signal Descriptions

Table 4-1

describes the signals for all device variants and package options.

Table 4-1. Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

YFF

RHA

General-purpose digital I/O pin

P1.0/TACLK/ADC10CLK

I/O

Timer_A, clock signal TACLK input

ADC10, conversion clock

General-purpose digital I/O pin

P1.1/TA0

I/O

Timer_A, capture: CCI0A input, compare: OUT0 output; BSL transmit

General-purpose digital I/O pin

P1.2/TA1

I/O

Timer_A, capture: CCI1A input, compare: OUT1 output

General-purpose digital I/O pin

P1.3/TA2

I/O

Timer_A, capture: CCI2A input, compare: OUT2 output

General-purpose digital I/O pin

P1.4/SMCLK/TCK

I/O

SMCLK signal output

Test Clock input for device programming and test

General-purpose digital I/O pin

P1.5/TA0/TMS

I/O

Timer_A, compare: OUT0 output

Test Mode Select input for device programming and test

General-purpose digital I/O pin

P1.6/TA1/TDI/TCLK

I/O

Timer_A, compare: OUT1 output

Test Data Input or Test Clock Input for programming and test

General-purpose digital I/O pin

P1.7/TA2/TDO/TDI

(1)

I/O

Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test

General-purpose digital I/O pin

P2.0/ACLK/A0

I/O

ACLK output

ADC10, analog input A0

General-purpose digital I/O pin

P2.1/TAINCLK/

I/O

Timer_A, clock signal at INCLK, SMCLK signal output

SMCLK/A1

ADC10, analog input A1

General-purpose digital I/O pin

P2.2/TA0/A2

I/O

Timer_A, capture: CCI0B input; BSL receive, compare: OUT0 output

ADC10, analog input A2

General-purpose digital I/O pin

Timer_A, capture CCI1B input, compare: OUT1 output

P2.3/TA1/A3/ V

REF-

eREF-

I/O

ADC10, analog input A3

Negative reference voltage output/input

General-purpose digital I/O pin

Timer_A, compare: OUT2 output

P2.4/TA2/A4/

I/O

REF+

eREF+

ADC10, analog input A4

Positive reference voltage output/input

General-purpose digital I/O pin

P2.5/R

OSC

I/O

Input for external DCO resistor to define DCO frequency

(1)

TDO or TDI is selected via JTAG instruction.

Terminal Configuration and Functions

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MSP430G2744 MSP430G2544 MSP430G2444

Summary of Contents for MSP430G2744DA

Page 1: ..._B With Three Capture Compare Package Options Registers TSSOP 38 Pin DA Universal Serial Communication Interface USCI QFN 40 Pin RHA Enhanced UART Supports Automatic Baud DSBGA 49 Pin YFF Rate Detecti...

Page 2: ...play or for transmission to a host system Stand alone radio frequency RF sensor front ends are another area of application Device Information 1 PART NUMBER PACKAGE BODY SIZE 2 MSP430G2744DA TSSOP 38 1...

Page 3: ...7 Bootstrap Loader BSL 43 5 8 Leakage Current Ports Px 17 6 8 Flash Memory 43 5 9 Outputs Ports Px 17 6 9 Peripherals 44 5 10 Output Frequency Ports Px 17 6 10 Oscillator and System Clock 44 5 11 Typ...

Page 4: ...bering 1 Added Device Information table 2 Added Section 3 moved and renamed Table 3 1 5 Corrected size of RAM for MSP430G2744 in Table 3 1 5 Added Section 5 and moved all electrical specifications to...

Page 5: ...544IRHA40 32 40 QFN HF LF MSP430G2544IDA38 1 1 16 512 TA3 TB3 12 1 DCO 32 38 TSSOP VLO MSP430G2544IYFF 32 49 DSBGA MSP430G2444IRHA40 32 40 QFN HF LF MSP430G2444IDA38 1 1 8 512 TA3 TB3 12 1 DCO 32 38 T...

Page 6: ...CLK 30 P2 4 TA2 A4 VREF VeREF 29 P2 3 TA1 A3 VREF VeREF 28 P3 7 A7 27 P3 6 A6 26 P3 5 UCA0RXD UCA0SOMI 25 P3 4 UCA0TXD UCA0SIMO 24 23 AVCC 22 AVSS 21 P4 7 TBCLK 20 P4 6 TBOUTH A15 DVSS P4 5 TB2 A14 MS...

Page 7: ...A0 32 P1 0 TACLK ADC10CLK 31 P2 4 TA2 A4 VREF VeREF 30 P2 3 TA1 A3 VREF VeREF 29 P3 7 A7 28 P3 6 A6 27 P3 5 UCA0RXD UCA0SOMI 26 P3 4 UCA0TXD UCA0SIMO 25 24 AVCC 23 AVSS 22 P4 7 TBCLK 21 P4 6 TBOUTH A1...

Page 8: ...I P2 3 TA1 A3 VREF VeREF P3 7 A7 P3 6 A6 P3 5 UCA0RXD UCA0SOMI P3 4 UCA0TXD UCA0SIMO AVCC AVSS P3 2 UCB0SOMI UCB0SCL P3 3 UCB0CLK UCA0STE P4 0 TB0 P4 1 TB1 P4 2 TB2 P4 3 TB0 A12 P4 4 TB1 A13 P4 5 TB2...

Page 9: ...B4 B3 B5 B6 B7 C1 C2 C4 C3 C5 C6 C7 D1 D2 D4 D3 D5 D6 D7 E1 E2 E4 E3 E5 E6 E7 F1 F2 F4 F3 F5 F6 F7 G1 G2 G4 G3 G5 G6 G7 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 1 P2 3 P2 4 P2 5 P3 0 P3 3 P3 4 P3 5...

Page 10: ...1 output Test Data Input or Test Clock Input for programming and test General purpose digital I O pin P1 7 TA2 TDO TDI 1 D2 38 40 36 I O Timer_A compare OUT2 output Test Data Output or Test Data Input...

Page 11: ...in P3 5 UCA0RXD G5 26 28 24 I O USCI_A0 receive data input in UART mode UCA0SOMI USCI_A0 slave out master in SPI mode General purpose digital I O pin P3 6 A6 F4 27 29 25 I O ADC10 analog input A6 Gene...

Page 12: ...Bi Wire test data input output during programming and test Selects test mode for JTAG pins on Port 1 The device protection fuse is connected to TEST TEST SBWTCK D1 1 1 37 I Spy Bi Wire test clock inpu...

Page 13: ...may be applied during board soldering process according to the current JEDEC J STD 020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes...

Page 14: ...MHz MSP430G2744 MSP430G2544 MSP430G2444 SLAS892C MARCH 2013 REVISED SEPTEMBER 2014 www ti com NOTE Minimum processor frequency is defined by system clock Flash program or erase operations require a mi...

Page 15: ...NIT fDCO fMCLK fSMCLK 1 MHz 2 2 V 270 fACLK 32768 Hz Program executes in flash Active mode AM IAM 1MHz BCSCTL1 CALBC1_1MHZ A current 1 MHz 3 V 390 550 DCOCTL CALDCO_1MHZ CPUOFF 0 SCG0 0 SCG1 0 OSCOFF...

Page 16: ...25 C 2 2 V 1 2 A LPM3 current 4 CPUOFF 1 SCG0 1 SCG1 1 OSCOFF 0 fDCO fMCLK fSMCLK 0 MHz fACLK from internal LF oscillator Low power mode 3 ILPM3 VLO VLO 25 C 2 2 V 0 5 1 A current LPM3 4 CPUOFF 1 SCG...

Page 17: ...y The port pin is selected for input and the pullup or pulldown resistor is disabled 5 9 Outputs Ports Px over recommended ranges of supply voltage and operating free air temperature unless otherwise...

Page 18: ...0 30 0 40 0 50 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VCC 3 V P4 5 TA 25 C TA 85 C OL I Typical Low Level Output Current mA MSP430G2744 MSP430G2544 MSP430G2444 SLAS892C MARCH 2013 REVISED SEPTEMBER 2014 ww...

Page 19: ...2000 s Pulse duration needed at RST NMI pin to t reset 2 2 V 2 s accept reset internally 1 The current consumption of the brownout module is already included in the ICC current consumption data The v...

Page 20: ...3 V MSP430G2744 MSP430G2544 MSP430G2444 SLAS892C MARCH 2013 REVISED SEPTEMBER 2014 www ti com 5 13 Typical Characteristics POR and BOR Figure 5 9 VCC drop Level With a Square Voltage Drop to Generate...

Page 21: ...ncy 7 3 RSELx 7 DCOx 3 MODx 0 3 V 0 80 1 50 MHz fDCO 8 3 DCO frequency 8 3 RSELx 8 DCOx 3 MODx 0 3 V 1 6 MHz fDCO 9 3 DCO frequency 9 3 RSELx 9 DCOx 3 MODx 0 3 V 2 3 MHz fDCO 10 3 DCO frequency 10 3 R...

Page 22: ...C1_8MHZ 8 MHz tolerance overall DCOCTL CALDCO_8MHZ 40 C to 85 C 2 2 V to 3 6 V 6 3 6 calibrated at 30 C and 3 V BCSCTL1 CALBC1_12MHZ 12 MHz tolerance over DCOCTL CALDCO_12MHZ 0 C to 85 C 3 V 3 0 5 3 t...

Page 23: ...from LPM3 or LPM4 1 DCOCTL CALDCO_1MHZ CPU wake up time from 1 fMCLK tCPU LPM3 4 LPM3 or LPM4 2 tClock LPM3 4 1 The DCO clock wake up time is measured from the edge of an external wake up signal for...

Page 24: ...of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DCOR 1 2 2 V 1 8 fDCO ROSC DCO output frequency with ROSC RSELx 4 DCOx 3 MODx...

Page 25: ...XOUT pins If conformal coating is used make sure that it does not induce capacitive or resistive leakage between the oscillator pins Do not route the XOUT line to the JTAG header to support the seria...

Page 26: ...the crystal as short as possible Design a good ground plane around the oscillator pins Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT Avoid running PCB traces under...

Page 27: ...LFXT1Sx 3 LFXT1Sx 2 MSP430G2744 MSP430G2544 MSP430G2444 www ti com SLAS892C MARCH 2013 REVISED SEPTEMBER 2014 5 23 Typical Characteristics LFXT1 Oscillator in HF Mode XTS 1 CL eff 15 pF TA 25 C CL eff...

Page 28: ...ommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal SMCLK ACLK fUSCI USCI input clock frequency External...

Page 29: ...SCI USCI input clock frequency SMCLK duty cycle 50 10 fSYSTEM MHz tSU MI SOMI input data setup time 3 V 75 ns tHD MI SOMI input data hold time 3 V 0 ns tVALID MO SIMO output data valid time UCLK edge...

Page 30: ...STE LAG STE lag time Last clock to STE high 3 V 10 ns tSTE ACC STE access time STE low to SOMI data out 3 V 50 ns STE disable time STE high to SOMI high tSTE DIS 3 V 50 ns impedance tSU SI SIMO input...

Page 31: ...xternal UCLK fSYSTEM MHz Duty cycle 50 10 fSCL SCL clock frequency 3 V 0 400 kHz fSCL 100 kHz 4 tHD STA Hold time repeated START 3 V s fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time for a repeat...

Page 32: ...nt with 25 C 3 V 1 1 mA REF2_5V 0 REFOUT 1 ADC10SR 0 4 ADC10SR 0 fADC10CLK 5 MHz Reference buffer supply ADC10ON 0 REFON 1 IREFB 1 current with 25 C 3 V 0 5 mA REF2_5V 0 REFOUT 1 ADC10SR 1 4 ADC10SR 1...

Page 33: ...oad regulation LSB IVREF 500 A 100 A Analog input voltage VAx 1 25 V 3 V 2 REF2_5V 1 IVREF 100 A to 900 A VREF load regulation VAx 0 5 x VREF 3 V 400 ns response time Error of conversion result 1 LSB...

Page 34: ...ternal reference is internally buffered The reference buffer is active and requires the reference buffer supply current IREFB The current consumption can be limited to the sample and conversion period...

Page 35: ...V C Sample time required if ADC10ON 1 INCHx 0Ah tSENSOR sample 3 V 30 s channel 10 is selected 3 Error of conversion result 1 LSB Current into divider at IVMID ADC10ON 1 INCHx 0Bh 3 V 3 A channel 11 A...

Page 36: ...r each additional byte or tBlock 1 63 2 18 tFTG word tBlock End Block program end sequence wait time 2 6 tFTG tMass Erase Mass erase time 2 10593 tFTG tSeg Erase Segment erase time 2 4819 tFTG 1 The c...

Page 37: ...re interface need to wait for the maximum tSBW En time after pulling the TEST SBWTCK pin high before applying the first SBWTCK clock edge 2 fTCK may be restricted to meet the timing requirements of th...

Page 38: ...plication All operations other than program flow instructions are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destinati...

Page 39: ...ation only CALL R8 PC TOS R8 PC Relative jump unconditional conditional JNE Jump on equal bit 0 Table 6 2 Address Mode Descriptions ADDRESS MODE S 1 D 2 SYNTAX EXAMPLE OPERATION Register MOV Rs Rd MOV...

Page 40: ...isabled ACLK and SMCLK remain active MCLK is disabled Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain active MCLK is disabled DCO dc generator is disabled if DCO not used in active mode Lo...

Page 41: ...Receive UCA0RXIFG UCB0RXIFG 2 maskable 0FFEEh 23 USCI_A0 or USCI_B0 Transmit UCA0TXIFG UCB0TXIFG 2 maskable 0FFECh 22 ADC10 ADC10IFG 4 maskable 0FFEAh 21 0FFE8h 20 I O Port P2 P2IFG 0 to P2IFG 7 2 4...

Page 42: ...B0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw 0 rw 0 rw 0 rw 0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 tr...

Page 43: ...MSP430 Programming Via the Bootstrap Loader User s Guide SLAU319 Table 6 9 BSL Function Pins BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS Data transmit 32 P1 1 30 P1 1 G3 P1 1 Data...

Page 44: ...ent A DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS CALBC1_1MHZ byte 010FFh 1 MHz CALDCO_1MHZ byte 010FEh CALBC1_8MHZ byte 010FDh 8 MHz CALDCO_8MHZ byte 010FCh CALBC1_12MHZ byte 010FBh 12 MHz CALDCO...

Page 45: ...ACLK Timer NA ACLK ACLK SMCLK SMCLK 9 P2 1 11 P2 1 7 P2 1 B4 P2 1 TAINCLK INCLK 32 P1 1 34 P1 1 30 P1 1 G2 P1 1 TA0 CCI0A CCR0 TA0 32 P1 1 34 P1 1 30 P1 1 G2 P1 1 10 P2 2 12 P2 2 8 P2 2 A5 P2 2 TA0 CC...

Page 46: ...1 D7 P4 1 21 P4 4 23 P4 4 19 P4 4 F7 P4 4 TB1 CCI1B 21 P4 4 23 P4 4 19 P4 4 F7 P4 4 VSS GND VCC VCC 19 P4 2 21 P4 2 17 P4 2 E6 P4 2 TB2 CCI2A CCR2 TB2 19 P4 2 21 P4 2 17 P4 2 E6 P4 2 ACLK CCI2B 22 P4...

Page 47: ...compare register TBCCR1 0194h Capture compare register TBCCR0 0192h Timer_B register TBR 0190h Capture compare control TBCCTL2 0186h Capture compare control TBCCTL1 0184h Capture compare control TBCCT...

Page 48: ...e control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh Basic Clock System Basic clock system control 3 BCSCTL3 053h Basic clock system co...

Page 49: ...nable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Special Function SFR interrupt...

Page 50: ...Output With Schmitt Trigger Table 6 15 Port P1 P1 0 to P1 3 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P1 x x FUNCTION P1DIR x P1SEL x P1 0 1 I 0 O 1 0 P1 0 TACLK ADC10CLK 0 Timer_A3 TACLK 0 1 ADC...

Page 51: ...ith Schmitt Trigger and In System Access Features Table 6 16 Port P1 P1 4 to P1 6 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P1 x x FUNCTION P1DIR x P1SEL x 4 Wire JTAG P1 4 2 I O I 0 O 1 0 0 P1...

Page 52: ...2014 www ti com 6 19 3 Port P1 Pin Schematic P1 7 Input Output With Schmitt Trigger and In System Access Features Table 6 17 Port P1 P1 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P1 x x FUNCT...

Page 53: ...able 6 18 Port P2 P2 0 P2 2 Pin Functions CONTROL BITS OR SIGNALS 1 Pin Name P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2 0 2 I O I 0 O 1 0 0 P2 0 ACLK A0 0 0 ACLK 1 1 0 A0 3 X X 1 P2 2 2 I O I 0 O...

Page 54: ...utput With Schmitt Trigger Table 6 19 Port P2 P2 1 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2 1 2 I O I 0 O 1 0 0 Timer_A3 INCLK 0 1 0 P2 1 TAINCL...

Page 55: ...ut Output With Schmitt Trigger Table 6 20 Port P2 P2 3 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2 3 2 I O I 0 O 1 0 0 Timer_A3 CCI1B 0 1 0 P2 3 TA...

Page 56: ...matic P2 4 Input Output With Schmitt Trigger Table 6 21 Port P2 P2 4 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x y FUNCTION P2DIR x P2SEL x ADC10AE0 y P2 4 2 I O I 0 O 1 0 0 P2 4 TA2 A4 4...

Page 57: ...014 6 19 8 Port P2 Pin Schematic P2 5 Input Output With Schmitt Trigger and External ROSC for DCO Table 6 22 Port P2 P2 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x FUNCTION P2DIR x P2SEL...

Page 58: ...2544 MSP430G2444 SLAS892C MARCH 2013 REVISED SEPTEMBER 2014 www ti com 6 19 9 Port P2 Pin Schematic P2 6 Input Output With Schmitt Trigger and Crystal Oscillator Input Table 6 23 Port P2 P2 6 Pin Func...

Page 59: ...10 Port P2 Pin Schematic P2 7 Input Output With Schmitt Trigger and Crystal Oscillator Output Table 6 24 Port P2 P2 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P2 x x FUNCTION P2DIR x P2SEL x...

Page 60: ...ADC10AE0 y P3 0 2 I O I 0 O 1 0 0 P3 0 UCB0STE 0 5 UCB0STE UCA0CLK 3 4 X 1 0 UCA0CLK A5 A5 5 X X 1 1 X Don t care 2 Default after reset PUC POR 3 The pin direction is controlled by the USCI module 4 U...

Page 61: ...I 0 O 1 0 P3 1 UCB0SIMO UCB0SDA 1 UCB0SIMO UCB0SDA 3 X 1 P3 2 2 I O I 0 O 1 0 P3 2 UCB0SOMI UCB0SCL 2 UCB0SOMI UCB0SCL 3 X 1 P3 3 2 I O I 0 O 1 0 P3 3 UCB0CLK UCA0STE 3 UCB0CLK UCA0STE 3 4 X 1 P3 4 2...

Page 62: ...6 27 Port P3 P3 6 P3 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P3 x x y FUNCTION P3DIR x P3SEL x ADC10AE0 y P3 6 2 I O I 0 O 1 0 0 P3 6 A6 6 6 A6 3 X X 1 P3 7 2 I O I 0 O 1 0 0 P3 7 A7 7 7 A7...

Page 63: ...atic P4 0 to P4 2 Input Output With Schmitt Trigger Table 6 28 Port P4 P4 0 to P4 2 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P4 x x FUNCTION P4DIR x P4SEL x P4 0 1 I O I 0 O 1 0 P4 0 TB0 0 Timer...

Page 64: ...t P4 P4 3 to P4 4 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P4 x x y FUNCTION P4DIR x P4SEL x ADC10AE1 y P4 3 2 I O I 0 O 1 0 0 Timer_B3 CCI0B 0 1 0 P4 3 TB0 A12 3 4 Timer_B3 TB0 1 1 0 A12 3 X...

Page 65: ...5 Input Output With Schmitt Trigger Table 6 30 Port P4 P4 5 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P4 x x y FUNCTION P4DIR x P4SEL x ADC10AE1 y P4 5 2 I O I 0 O 1 0 0 P4 5 TB3 A14 5 6 Timer_...

Page 66: ...le 6 31 Port P4 P4 6 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P4 x x y FUNCTION P4DIR x P4SEL x ADC10AE1 y P4 6 2 I O I 0 O 1 0 0 TBOUTH 0 1 0 P4 6 TBOUTH A15 6 7 DVSS 1 1 0 A15 3 X X 1 1 X Do...

Page 67: ...TEMBER 2014 6 19 18 Port P4 Pin Schematic P4 7 Input Output With Schmitt Trigger Table 6 32 Port P4 Pr 7 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P4 x x FUNCTION P4DIR x P4SEL x P4 7 1 I O I 0 O...

Page 68: ...e fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is held low during power up The second positive edge on the TMS pin deactivates the fuse check mode After...

Page 69: ...ded The following table shows the compatible target boards and the supported packages Package Target Board and Programmer Bundle Target Board Only 38 pin TSSOP DA MSP FET430U38 MSP TS430DA38 7 1 2 2 2...

Page 70: ...t is not necessarily representative of the final device s electrical specifications PMS Final silicon die that conforms to the device s electrical specifications but has not completed quality and reli...

Page 71: ...ies Optional A Revision N A Optional Temperature Range S 0 C to 50 C C to 70 C I 40 C to 85 C T 40 C to 105 C C 0 Packaging www ti com packaging Optional Tape and Reel T Small Reel 7 inch R Large Reel...

Page 72: ...re provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Community TI s Engineer to Engineer E2E...

Page 73: ...information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet ref...

Page 74: ...ACTIVE TSSOP DA 38 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 M430G2544 MSP430G2544IRHA40R ACTIVE VQFN RHA 40 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430...

Page 75: ...l category on the device 5 Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it...

Page 76: ...8 2000 330 0 24 4 8 6 13 0 1 8 12 0 24 0 Q1 MSP430G2544IRHA40R VQFN RHA 40 2500 330 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430G2544IRHA40R VQFN RHA 40 2500 330 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430G2544I...

Page 77: ...TSSOP DA 38 2000 367 0 367 0 45 0 MSP430G2544IRHA40R VQFN RHA 40 2500 367 0 367 0 38 0 MSP430G2544IRHA40R VQFN RHA 40 2500 367 0 367 0 35 0 MSP430G2544IRHA40T VQFN RHA 40 250 210 0 185 0 35 0 MSP430G...

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Page 80: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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