SDA
SCL
1/fSCL
tHD,DAT
tSU,DAT
tHD,STA
tSU,STA tHD,STA
tSU,STO
tSP
MSP430G2744, MSP430G2544, MSP430G2444
www.ti.com
SLAS892C – MARCH 2013 – REVISED SEPTEMBER 2014
5.28 USCI (I
2
C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-22
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency
External: UCLK
f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency
3 V
0
400
kHz
f
SCL
≤
100 kHz
4
t
HD,STA
Hold time (repeated) START
3 V
µs
f
SCL
> 100 kHz
0.6
f
SCL
≤
100 kHz
4.7
t
SU,STA
Setup time for a repeated START
3 V
µs
f
SCL
> 100 kHz
0.6
t
HD,DAT
Data hold time
3 V
0
ns
t
SU,DAT
Data setup time
3 V
250
ns
t
SU,STO
Setup time for STOP
3 V
4
µs
Pulse duration of spikes suppressed by
t
SP
3 V
50
100
600
ns
input filter
Figure 5-22. I
2
C Mode Timing
Copyright © 2013–2014, Texas Instruments Incorporated
Specifications
31
Submit Documentation Feedback
Product Folder Links:
MSP430G2744 MSP430G2544 MSP430G2444
