MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C – MARCH 2013 – REVISED SEPTEMBER 2014
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5.24 Timer_A, Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
f
TA
Timer_A clock frequency
SMCLK, Duty cycle = 50% ± 10%
f
SYSTEM
MHz
t
TA,cap
Timer_A capture timing
TAx, TBx
3 V
20
ns
5.25 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency
External: UCLK
f
SYSTEM
MHz
Duty cycle = 50% ± 10%
Maximum BITCLK clock frequency
f
max,BITCLK
3 V
2
MHz
(equals baud rate in MBaud)
t
τ
UART receive deglitch time
(1)
3 V
50
100
600
ns
(1)
The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
28
Specifications
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