UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI
tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI
tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
MSP430G2744, MSP430G2544, MSP430G2444
www.ti.com
SLAS892C – MARCH 2013 – REVISED SEPTEMBER 2014
5.26 USCI (SPI Master Mode)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see
Figure 5-18
and
Figure 5-19
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
f
USCI
USCI input clock frequency
SMCLK, duty cycle = 50% ± 10%
f
SYSTEM
MHz
t
SU,MI
SOMI input data setup time
3 V
75
ns
t
HD,MI
SOMI input data hold time
3 V
0
ns
t
VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid,C
L
= 20 pF
3 V
20
ns
(1)
f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥
max(t
VALID,MO(USCI)
+ t
SU,SI(Slave)
, t
SU,MI(USCI)
+ t
VALID,SO(Slave)
).
For the slave parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
, see the SPI parameters of the attached slave.
Figure 5-18. SPI Master Mode, CKPH = 0
Figure 5-19. SPI Master Mode, CKPH = 1
Copyright © 2013–2014, Texas Instruments Incorporated
Specifications
29
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