Texas Instruments MSP430G2203 Datasheet Download Page 10

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MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G – APRIL 2011 – REVISED APRIL 2016

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MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

MSP430G2203

Terminal Configuration and Functions

(1)

MSP430G2x33 devices only

4.2

Signal Descriptions

Table 4-1

describes the signals.

Table 4-1. Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PW20,

N20

PW28

RHB32

P1.0/

I/O

General-purpose digital I/O pin

TA0CLK/

Timer0_A, clock signal TACLK input

ACLK/

ACLK signal output

ADC10 analog input A0

(1)

P1.1/

I/O

General-purpose digital I/O pin

TA0.0/

Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit

UCA0RXD/

USCI_A0 receive data input in UART mode

UCA0SOMI/

USCI_A0 slave data out/master in SPI mode

ADC10 analog input A1

(1)

P1.2/

I/O

General-purpose digital I/O pin

TA0.1/

Timer0_A, capture: CCI1A input, compare: Out1 output

UCA0TXD/

USCI_A0 transmit data output in UART mode

UCA0SIMO/

USCI_A0 slave data in/master out in SPI mode

ADC10 analog input A2

(1)

P1.3/

I/O

General-purpose digital I/O pin

ADC10CLK/

ADC10, conversion clock output

(1)

A3/

ADC10 analog input A3

(1)

VREF-/VEREF-

ADC10 negative reference voltage

(1)

P1.4/

I/O

General-purpose digital I/O pin

SMCLK/

SMCLK signal output

UCB0STE/

USCI_B0 slave transmit enable

UCA0CLK/

USCI_A0 clock input/output

A4/

ADC10 analog input A4

(1)

VREF+/VEREF+

ADC10 positive reference voltage

(1)

TCK

JTAG test clock, input terminal for device programming and test

P1.5/

I/O

General-purpose digital I/O pin

TA0.0/

Timer0_A, compare: Out0 output / BSL receive

UCB0CLK/

USCI_B0 clock input/output

UCA0STE/

USCI_A0 slave transmit enable

A5/

ADC10 analog input A5

(1)

TMS

JTAG test mode select, input terminal for device programming and test

P1.6/

I/O

General-purpose digital I/O pin

TA0.1/

Timer0_A, compare: Out1 output

A6/

ADC10 analog input A6

(1)

UCB0SOMI/

USCI_B0 slave out/master in SPI mode,

UCB0SCL/

USCI_B0 SCL I

C clock in I

C mode

TDI/TCLK

JTAG test data input or test clock input during programming and test

Summary of Contents for MSP430G2203

Page 1: ...old and Autoscan See Table 3 1 Brownout Detector Serial Onboard Programming No External Programming Voltage Needed Programmable Code Protection by Security Fuse On Chip Emulation Logic With Spy Bi Wire Interface Section 3 Summarizes Available Family Members Package Options TSSOP 20 Pin 28 Pin PDIP 20 Pin QFN 32 Pin For Complete Module Descriptions See the MSP430x2xx Family User s Guide SLAU144 1 2...

Page 2: ... 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Device Overview Copyright 2011 2016 Texas Instruments Incorporated 1 For the most current part package and ordering information see the Package Option Addendum in Section 8 or see the TI website at www ti com 2 The sizes shown he...

Page 3: ...ash 8KB 4KB 2KB USCI A0 UART LIN IrDA SPI USCI B0 SPI I C 2 MDB MAB Copyright 2016 Texas Instruments Incorporated 3 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 www ti com SLAS734G APRIL 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Device Overview...

Page 4: ... 5 17 Main DCO Characteristics 24 5 18 DCO Frequency 24 5 19 Calibrated DCO Frequencies Tolerance 25 5 20 Wake up Times From Lower Power Modes LPM3 LPM4 26 5 21 Typical Characteristics DCO Clock Wake up Time From LPM3 or LPM4 26 5 22 Crystal Oscillator XT1 Low Frequency Mode 27 5 23 Internal Very Low Power Low Frequency Oscillator VLO 27 5 24 Timer_A 27 5 25 USCI UART Mode 28 5 26 USCI SPI Master ...

Page 5: ...on of section numbering 1 Added Device Information table 2 Added Section 3 1 Related Products 7 Moved Section 5 Specifications 13 Added Section 5 2 ESD Ratings 13 Added Section 5 8 Thermal Resistance Characteristics 18 Throughout document changed all instances of bootstrap loader to bootloader 39 Changed all instances of INCHx 0x1010 to INCHx 1010b in Table 6 11 Labels Used by the ADC Calibration ...

Page 6: ...ison Table 3 1 compares the available family members Table 3 1 Device Comparison 1 2 DEVICE BSL EEM FLASH KB RAM B Timer_A ADC10 CHANNELS USCI_A0 USCI_B0 CLOCK I O PACKAGE MSP430G2533 1 1 16 512 2x TA3 8 1 LF DCO VLO 24 32 QFN 24 28 TSSOP 16 20 TSSOP 16 20 PDIP MSP430G2433 1 1 8 512 2x TA3 8 1 LF DCO VLO 24 32 QFN 24 28 TSSOP 16 20 TSSOP 16 20 PDIP MSP430G2333 1 1 4 256 2x TA3 8 1 LF DCO VLO 24 32...

Page 7: ...CUs from Texas Instruments TI offer the lowest power consumption and the perfect mix of integrated peripherals for a wide range of low power and portable applications Products for MSP430G2x i2x Low Cost Industrial MCUs MSP430G2x microcontrollers MCUs from the MSP ultra low power MCU series offers the low power and performance of 16 bit MSP microcontrollers with a feature set targeted at cost sensi...

Page 8: ... A1 UCA0RXD UCA0SOMI P1 2 TA0 1 A2 UCA0TXD UCA0SIMO P1 4 SMCLK TCK VREF VEREF A4 UCB0STE UCA0CLK P1 5 TA0 0 A5 TMS UCB0CLK UCA0STE N20 PW20 TOP VIEW 8 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP4...

Page 9: ...CA0CLK P1 5 TA0 0 A5 TMS UCB0CLK UCA0STE P1 6 TA0 1 TDI TCLK UCB0SOMI UCB0SCL A6 P1 7 TDO TDI UCB0SIMO UCB0SDA A7 9 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 www ti com SLAS734G APRIL 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Terminal Config...

Page 10: ..._A capture CCI1A input compare Out1 output UCA0TXD USCI_A0 transmit data output in UART mode UCA0SIMO USCI_A0 slave data in master out in SPI mode A2 ADC10 analog input A2 1 P1 3 5 5 3 I O General purpose digital I O pin ADC10CLK ADC10 conversion clock output 1 A3 ADC10 analog input A3 1 VREF VEREF ADC10 negative reference voltage 1 P1 4 6 6 4 I O General purpose digital I O pin SMCLK SMCLK signal...

Page 11: ...TA1 1 Timer1_A capture CCI1B input compare Out1 output P2 3 11 16 15 I O General purpose digital I O pin TA1 0 Timer1_A capture CCI0B input compare Out0 output P2 4 12 17 16 I O General purpose digital I O pin TA1 2 Timer1_A capture CCI2A input compare Out2 output P2 5 13 18 17 I O General purpose digital I O pin TA1 2 Timer1_A capture CCI2B input compare Out2 output XIN 19 27 26 I O Input termina...

Page 12: ...ht 2011 2016 Texas Instruments Incorporated Table 4 1 Terminal Functions continued TERMINAL I O DESCRIPTION NAME NO PW20 N20 PW28 RHB32 TEST 17 25 24 I Selects test mode for JTAG pins on Port 1 The device protection fuse is connected to TEST SBWTCK Spy Bi Wire test clock input during programming and test AVCC NA NA 29 NA Analog supply voltage DVCC 1 1 30 NA Digital supply voltage DVSS 20 28 27 28 ...

Page 13: ...d at VCC to VSS 0 3 4 1 V Voltage applied to any pin 2 0 3 VCC 0 3 V Diode current at any device pin 2 mA Storage temperature Tstg 3 Unprogrammed device 55 150 C Programmed device 55 150 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process Pins listed as 1000 V may actually have higher performance 2 JEDEC document JEP157 states that 250 V CDM ...

Page 14: ...ck Flash program or erase operations require a minimum VCC of 2 2 V Figure 5 1 Safe Operating Area 1 All inputs are tied to 0 V or to VCC Outputs do not source or sink any current 2 The currents are characterized with a Micro Crystal CC4V T1A SMD crystal with a load capacitance of 9 pF The internal and external load capacitance is chosen to closely match the required 9 pF 5 4 Active Mode Supply Cu...

Page 15: ...G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 www ti com SLAS734G APRIL 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright 2011 2016 Texas Instruments Incorporated 5 5 Typical Characteristics Active Mode Supply Current Into VCC Figure ...

Page 16: ...ly Currents Into VCC Excluding External Current over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 2 PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT ILPM0 1MHz Low power mode 0 LPM0 current 3 fMCLK 0 MHz fSMCLK fDCO 1 MHz fACLK 32768 Hz BCSCTL1 CALBC1_1MHZ DCOCTL CALDCO_1MHZ CPUOFF 1 SCG0 0 SCG1 0 OSCOFF 0 25 C 2 2 V 56 µA ILPM2 Low power mode 2...

Page 17: ...SP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 www ti com SLAS734G APRIL 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright 2011 2016 Texas Instruments Incorporated 5 7 Typical Characteristics Low Power Mode Supply Currents over recommended ra...

Page 18: ...C standard High K board as specified in JESD51 7 in an environment described in JESD51 2a 3 The junction to case top thermal resistance is obtained by simulating a cold plate test on the package top No specific JEDEC standard test exists but a close description can be found in the ANSI SEMI standard G30 88 4 The junction to board thermal resistance is obtained by simulating in an environment with ...

Page 19: ... for input and the pullup pulldown resistor is disabled 5 10 Leakage Current Ports Px over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg Px y High impedance leakage current See 1 2 3 V 50 nA 1 The maximum total current I OHmax and I OLmax for all outputs combined should not exceed 48 mA to hold the max...

Page 20: ...20 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright 2011 2016 Texas Instruments Incorporated 5 13 Typical Characteristics Outputs over recommended ranges o...

Page 21: ...ed to the center tap of the divider 2 The output voltage reaches at least 10 and 90 VCC at the specified toggle frequency 5 14 Pin Oscillator Frequency Ports Px over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT foP1 x Port output oscillation frequency P1 y CL 10 pF RL 100 kΩ 1 2 3 V 1400 kHz P1 y CL 20...

Page 22: ...B_IT Vhys B_IT is 1 8 V 2 During power up the CPU begins code execution following a period of td BOR after VCC V B_IT Vhys B_IT The default DCO settings must not be changed until VCC VCC min where VCC min is the minimum supply voltage for the desired operating frequency 5 16 POR BOR 1 2 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TE...

Page 23: ...30G2233 MSP430G2403 MSP430G2303 MSP430G2203 www ti com SLAS734G APRIL 2011 REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Specifications Copyright 2011 2016 Texas Instruments Incorporated Figure 5 14 VCC drop Level With a Triangle Voltage Drop to Generate a POR or BOR Signal ...

Page 24: ... DCO frequency 0 3 RSELx 0 DCOx 3 MODx 0 3 V 0 07 0 17 MHz fDCO 1 3 DCO frequency 1 3 RSELx 1 DCOx 3 MODx 0 3 V 0 15 MHz fDCO 2 3 DCO frequency 2 3 RSELx 2 DCOx 3 MODx 0 3 V 0 21 MHz fDCO 3 3 DCO frequency 3 3 RSELx 3 DCOx 3 MODx 0 3 V 0 30 MHz fDCO 4 3 DCO frequency 4 3 RSELx 4 DCOx 3 MODx 0 3 V 0 41 MHz fDCO 5 3 DCO frequency 5 3 RSELx 5 DCOx 3 MODx 0 3 V 0 58 MHz fDCO 6 3 DCO frequency 6 3 RSEL...

Page 25: ...0 C to 85 C 1 8 V to 3 6 V 6 3 6 8 MHz tolerance over temperature 1 BCSCTL1 CALBC1_8MHZ DCOCTL CALDCO_8MHZ calibrated at 30 C and 3 V 0 C to 85 C 3 V 3 0 5 3 8 MHz tolerance over VCC BCSCTL1 CALBC1_8MHZ DCOCTL CALDCO_8MHZ calibrated at 30 C and 3 V 30 C 2 2 V to 3 6 V 3 2 3 8 MHz tolerance overall BCSCTL1 CALBC1_8MHZ DCOCTL CALDCO_8MHZ calibrated at 30 C and 3 V 40 C to 85 C 2 2 V to 3 6 V 6 3 6 1...

Page 26: ...f an external wake up signal for example port interrupt to the first clock edge observable externally on a clock pin MCLK or SMCLK 2 Parameter applicable only if DCOCLK is used for MCLK 5 20 Wake up Times From Lower Power Modes LPM3 LPM4 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tDCO LPM3 4 DCO...

Page 27: ...ation do not set the fault flag Frequencies in between might set the flag 4 Measured with logic level input frequency but also applies to operation with crystals 5 22 Crystal Oscillator XT1 Low Frequency Mode 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fLFXT1 LF LFXT1 oscillator crystal frequen...

Page 28: ...ir duration should exceed the maximum specification of the deglitch time 5 25 USCI UART Mode over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fUSCI USCI input clock frequency SMCLK duty cycle 50 10 fSYSTEM MHz fmax BITCLK Maximum BITCLK clock frequency equals baud rate in MBaud 1 3 V 2 MHz tτ UART rec...

Page 29: ...tions Copyright 2011 2016 Texas Instruments Incorporated 5 27 USCI SPI Slave Mode over recommended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 18 and Figure 5 19 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE LEAD STE lead time STE low to clock 3 V 50 ns tSTE LAG STE lag time Last clock to STE high 3 V 10 ns tSTE ACC STE access time STE low ...

Page 30: ... over recommended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 20 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fUSCI USCI input clock frequency SMCLK duty cycle 50 10 fSYSTEM MHz fSCL SCL clock frequency 3 V 0 400 kHz tHD STA Hold time repeated START fSCL 100 kHz 3 V 4 0 µs fSCL 100 kHz 0 6 tSU STA Setup time for a repeated START fSCL 100 kHz 3 ...

Page 31: ... 10 Bit ADC Power Supply and Input Range Conditions MSP430G2x33 Only over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT VCC Analog supply voltage VSS 0 V 2 2 3 6 V VAx Analog input voltage 2 All Ax terminals Analog inputs selected in ADC10AE register 3 V 0 VCC V IADC10 ADC10 supply current 3 fADC10...

Page 32: ...A REF2_5V 1 2 9 VREF Positive built in reference voltage IVREF IVREF max REF2_5V 0 3 V 1 41 1 5 1 59 V IVREF IVREF max REF2_5V 1 2 35 2 5 2 65 ILD VREF Maximum VREF load current 3 V 1 mA VREF load regulation IVREF 500 µA 100 µA Analog input voltage VAx 0 75 V REF2_5V 0 3 V 2 LSB IVREF 500 µA 100 µA Analog input voltage VAx 1 25 V REF2_5V 1 2 VREF load regulation response time IVREF 100 µA 900 µA V...

Page 33: ...METER TEST CONDITIONS VCC MIN TYP MAX UNIT VEREF Positive external reference input voltage range 2 VEREF VEREF SREF1 1 SREF0 0 1 4 VCC V VEREF VEREF VCC 0 15 V SREF1 1 SREF0 1 3 1 4 3 VEREF Negative external reference input voltage range 4 VEREF VEREF 0 1 2 V ΔVEREF Differential external reference input voltage range ΔVEREF VEREF VEREF VEREF VEREF 5 1 4 VCC V IVEREF Static input current into VEREF...

Page 34: ...sor sample Sample time required if channel 10 is selected 3 ADC10ON 1 INCHx 0Ah Error of conversion result 1 LSB 3 V 30 µs IVMID Current into divider at channel 11 ADC10ON 1 INCHx 0Bh 3 V 4 µA VMID VCC divider at channel 11 ADC10ON 1 INCHx 0Bh VMID 0 5 VCC 3 V 1 5 V tVMID sample Sample time required if channel 11 is selected 5 ADC10ON 1 INCHx 0Bh Error of conversion result 1 LSB 3 V 1220 ns 1 Do n...

Page 35: ...tricted to meet the timing requirements of the module selected 5 37 JTAG and Spy Bi Wire Interface over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER VCC MIN TYP MAX UNIT fSBW Spy Bi Wire input frequency 2 2 V 0 20 MHz tSBW Low Spy Bi Wire low clock pulse duration 2 2 V 0 025 15 µs tSBW En Spy Bi Wire enable time TEST high to acceptance of...

Page 36: ...P430 CPU has a 16 bit RISC architecture that is highly transparent to the application All operations other than program flow instructions are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand The CPU is integrated with 16 registers that provide reduced instruction execution time The register to register ...

Page 37: ... types of instruction formats Table 6 2 lists the address modes Table 6 1 Instruction Word Formats INSTRUCTION FORMAT EXAMPLE OPERATION Dual operands source destination ADD R4 R5 R4 R5 R5 Single operands destination only CALL R8 PC TOS R8 PC Relative jump unconditional or conditional JNE Jump on equal bit 0 1 S source D destination Table 6 2 Address Mode Descriptions ADDRESS MODE S 1 D SYNTAX EXAM...

Page 38: ... the low power mode on return from the interrupt program Software can configure the following operating modes Active mode AM All clocks are active Low power mode 0 LPM0 CPU is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain active MCLK is disabled DC generator of the DCO is disabled if DCO not used in active mode Low power mode 2 L...

Page 39: ...wer up starting address are in the address range 0FFFFh to 0FFC0h see Table 6 3 The vector contains the 16 bit address of the appropriate interrupt handler instruction sequence If the reset vector at address 0FFFEh contains 0FFFFh for example if the flash is not programmed the CPU goes into LPM4 immediately after power up Table 6 3 Interrupt Sources Flags and Vectors INTERRUPT SOURCE INTERRUPT FLA...

Page 40: ... NMIIE RW 0h Non maskable interrupt enable 1 OFIE RW 0h Oscillator fault interrupt enable 0 WDTIE RW 0h Watchdog Timer interrupt enable Inactive if watchdog mode is selected Active if Watchdog Timer is configured in interval timer mode Figure 6 3 Interrupt Enable Register 2 Address 01h 7 6 5 4 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw 0 rw 0 rw 0 rw 0 Table 6 5 Interrupt Enable Register 2 Des...

Page 41: ...n interrupt vector Flash FFFFh to FFC0h FFFFh to FFC0h FFFFh to FFC0h FFFFh to FFC0h Main code memory Flash FFFFh to F800h FFFFh to F000h FFFFh to E000h FFFFh to C000h Information memory Size 256 byte 256 byte 256 byte 256 byte Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h RAM Size 256 byte 256 byte 512 byte 512 byte 02FFh to 0200h 02FFh to 0200h 03FFh to 0200h 03FFh to...

Page 42: ...gainst programming and erasing It can be unlocked but care should be taken not to erase this segment if the device specific calibration data is required 6 9 Peripherals Peripherals are connected to the CPU through data address and control buses The peripherals can be managed using all instructions For complete module descriptions see the MSP430x2xx Family User s Guide SLAU144 6 9 1 Oscillator and ...

Page 43: ...2_5 1 TA 30 C IVREF 1 mA CAL_ADC_15T85 0x000A word INCHx 1010b REF2_5 0 TA 85 C CAL_ADC_15T30 0x0008 word INCHx 1010b REF2_5 0 TA 30 C CAL_ADC_15VREF_FACTOR 0x0006 word REF2_5 0 TA 30 C IVREF 0 5 mA CAL_ADC_OFFSET 0x0004 word External VREF 1 5 V fADC10CLK 5 MHz CAL_ADC_GAIN_FACTOR 0x0002 word External VREF 1 5 V fADC10CLK 5 MHz CAL_BC1_1MHZ 0x0009 byte CAL_DCO_1MHZ 0x0008 byte CAL_BC1_8MHZ 0x0007 ...

Page 44: ... counters with three capture compare registers Timer_A3 can support multiple capture compares PWM outputs and interval timing see Table 6 12 and Table 6 13 Timer_A3 also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Table 6 12 Timer0_A3 Signal Connections INPUT PIN NUMBER DEVICE INPUT SIGNAL M...

Page 45: ...11 TA1 1 CCI1B P2 2 10 P2 2 12 P2 2 11 VSS GND P3 2 13 P3 2 12 VCC VCC P2 4 12 P2 4 17 P2 4 16 TA1 2 CCI2A CCR2 TA2 P2 4 12 P2 4 17 P2 4 16 P2 5 13 P2 5 18 P2 5 17 TA1 2 CCI2B P2 5 13 P2 5 18 P2 5 17 VSS GND P3 3 14 P3 3 13 VCC VCC 6 9 7 Universal Serial Communications Interface USCI The USCI module is used for serial data communication The USCI module supports synchronous communication protocols ...

Page 46: ...L2 0186h Capture compare control TA1CCTL1 0184h Capture compare control TA1CCTL0 0182h Timer_A control TA1CTL 0180h Timer_A interrupt vector TA1IV 011Eh Timer0_A3 Capture compare register TA0CCR2 0176h Capture compare register TA0CCR1 0174h Capture compare register TA0CCR0 0172h Timer_A register TA0R 0170h Capture compare control TA0CCTL2 0166h Capture compare control TA0CCTL1 0164h Capture compar...

Page 47: ...r 1 ADC10DTC1 049h ADC data transfer control register 0 ADC10DTC0 048h Basic Clock System Basic clock system control 3 BCSCTL3 053h Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h Port P3 28 pin PW and 32 pin RHB only Port P3 selection 2 pin P3SEL2 043h Port P3 resistor enable P3REN 010h Port P3 selection P3SEL 01Bh Port P...

Page 48: ...rection 0 Input 1 Output PxSEL y 3 2 1 0 PxSEL2 y 0 48 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10...

Page 49: ...2 Pin Functions PIN NAME P1 x x FUNCTION CONTROL BITS OR SIGNALS 1 P1DIR x P1SEL x P1SEL2 x ADC10AE x INCH y 1 2 P1 0 0 P1 x I O I 0 O 1 0 0 0 TA0CLK TA0 TACLK 0 1 0 0 ACLK ACLK 1 1 0 0 A0 2 A0 X X X 1 y 0 Pin Osc Capacitive sensing X 0 1 0 P1 1 1 P1 x I O I 0 O 1 0 0 0 TA0 0 TA0 0 1 1 0 0 TA0 CCI0A 0 1 0 0 UCA0RXD UCA0RXD from USCI 1 1 0 UCA0SOMI UCA0SOMI from USCI 1 1 0 A1 2 A1 X X X 1 y 1 Pin O...

Page 50: ...t PxSEL y PxIES y PxIFG y ADC10AE0 y PxSEL2 y 50 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10 2 Por...

Page 51: ...SP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 1 X don t care 2 MSP430G2x33 devices only Table 6 17 Port P1 P1 3 Pin Functions PIN NAME P1 x x FUNCTION CONTROL BITS OR SIGNALS 1 P1DIR x P1SEL x P1SEL2 x ADC10AE x INCH y 1 2 P1 3 3 P1 x I O I 0 O 1 0 0 0 ADC10CLK 2 ADC10CLK 1 1 0 0 A3 2 A3 X X X 1 y 3 VREF 2 VREF X X X 1 VEREF 2 VEREF X X ...

Page 52: ...ces only MSP430G2x03 devices have no ADC10 from Module 52 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6...

Page 53: ... is controlled by the USCI module 4 UCA0CLK function takes precedence over UCB0STE function If the pin is required as UCA0CLK input or output USCI_B0 is forced to 3 wire SPI mode if 4 wire SPI mode is selected Table 6 18 Port P1 P1 4 Pin Functions PIN NAME P1 x x FUNCTION CONTROL BITS OR SIGNALS 1 P1DIR x P1SEL x P1SEL2 x ADC10AE x INCH y 1 2 JTAG Mode P1 4 4 P1 x I O I 0 O 1 0 0 0 0 SMCLK SMCLK 1...

Page 54: ... y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y ADC10AE0 y 54 MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 201...

Page 55: ...f 4 wire SPI mode is selected Table 6 19 Port P1 P1 5 to P1 7 Pin Functions PIN NAME P1 x x FUNCTION CONTROL BITS OR SIGNALS 1 P1DIR x P1SEL x P1SEL2 x ADC10AE x INCH y 1 2 JTAG Mode P1 5 5 P1 x I O I 0 O 1 0 0 0 0 TA0 0 TA0 0 1 1 0 0 0 UCB0CLK UCB0CLK 3 4 from USCI 1 1 0 0 UCA0STE UCA0STE 3 4 from USCI 1 1 0 0 A5 2 A5 X X X 1 y 5 0 TMS TMS X X X 0 1 Pin Osc Capacitive sensing X 0 1 0 0 P1 6 6 P1 ...

Page 56: ...P430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10 5 Port P2 Pin Diagram P2 0 to P2 5 Input Output With Schmitt Trigger...

Page 57: ...SEL x P2SEL2 x P2 0 0 P2 x I O I 0 O 1 0 0 TA1 0 Timer1_A3 CCI0A 0 1 0 Timer1_A3 TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P2 1 1 P2 x I O I 0 O 1 0 0 TA1 1 Timer1_A3 CCI1A 0 1 0 Timer1_A3 TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2 2 2 P2 x I O I 0 O 1 0 0 TA1 1 Timer1_A3 CCI1B 0 1 0 Timer1_A3 TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2 3 3 P2 x I O I 0 O 1 0 0 TA1 0 Timer1_A3 CCI0B 0 1 0 Ti...

Page 58: ... MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10 6 Port P2 Pin Diagram P2 6 Input Output With Schmitt ...

Page 59: ...P430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 1 X don t care Table 6 21 Port P2 P2 6 Pin Functions PIN NAME P2 x x FUNCTION CONTROL BITS OR SIGNALS 1 P2DIR x P2SEL 6 P2SEL 7 P2SEL2 6 P2SEL2 7 XIN 6 XIN 0 1 1 0 0 P2 6 P2 x I O I 0 O 1 0 X 0 0 TA0 1 Timer0_A3 TA1 1 1 0 0 0 Pin Osc Capacitive sensing X 0 X...

Page 60: ...MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10 7 Port P2 Pin Diagram P2 7 Input Output With Schmitt T...

Page 61: ...MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 1 X don t care Table 6 22 Port P2 P2 7 Pin Functions PIN NAME P2 x x FUNCTION CONTROL BITS OR SIGNALS 1 P2DIR x P2SEL 6 P2SEL 7 P2SEL2 6 P2SEL2 7 XOUT 7 XOUT 1 1 1 0 0 P2 7 P2 x I O I 0 O 1 0 X 0 0 Pin Osc Capacitive sensing X 0 X 1 X ...

Page 62: ...SP430G2303 MSP430G2203 SLAS734G APRIL 2011 REVISED APRIL 2016 www ti com Submit Documentation Feedback Product Folder Links MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 Detailed Description Copyright 2011 2016 Texas Instruments Incorporated 6 10 8 Port P3 Pin Diagram P3 0 to P3 7 Input Output With Schmitt Trigger RHB and PW28 Package Only Figure 6 13 shows th...

Page 63: ... P3 x I O I 0 O 1 0 0 TA0 2 Timer0_A3 CCI2A 0 1 0 Timer0_A3 TA2 1 1 0 Pin Osc Capacitive sensing X 0 1 P3 1 1 P3 x I O I 0 O 1 0 0 TA1 0 Timer1_A3 TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P3 2 2 P3 x I O I 0 O 1 0 0 TA1 1 Timer1_A3 TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P3 3 3 P3 x I O I 0 O 1 0 0 TA1 2 Timer1_A3 TA2 1 1 0 Pin Osc Capacitive sensing X 0 1 P3 4 4 P3 x I O I 0 O 1 0 0 TA0 0 Ti...

Page 64: ...lutionary flow XMS Experimental device that is not necessarily representative of the electrical specifications for the final device PMS Final silicon die that conforms to the electrical specifications for the device but has not completed quality and reliability verification MSP Fully qualified production device Support tool development evolutionary flow MSPX Development support product that has no...

Page 65: ...al Temperature Range S 0 C to 50 C C to 70 C I 40 C to 85 C T 40 C to 105 C C 0 Packaging http www ti com packaging Optional Tape and Reel T Small Reel R Large Reel No Markings Tube or Tray Optional Additional Features EP Enhanced Product 40 C to 105 C HT Extreme Temperature Parts 55 C to 150 C Q1 Automotive Q100 Qualified MSP 430 F 5 438 A I ZQW T EP Processor Family Series Optional Temperature R...

Page 66: ...lopment Kit is an easy to use microcontroller development board for the low power and low cost MSP430G2x MCUs It has on board emulation for programming and debugging and features a 14 or 20 pin DIP socket on board buttons and LEDs and BoosterPack Plug in Module pinouts that support a wide range of modules for added functionality such as wireless displays and more MSP430 Capacitive Touch BoosterPac...

Page 67: ...h and Qmath Libraries are a collection of highly optimized and high precision mathematical functions for C programmers to seamlessly port a floating point algorithm into fixed point code on MSP430 and MSP432 devices These routines are typically used in computationally intensive real time applications where optimal execution speed high accuracy and ultra low energy are critical By using the IQmath ...

Page 68: ...oard called the Gang Splitter that implements the interconnections between the MSP Gang Programmer and multiple target devices Eight cables are provided that connect the expansion board to eight target devices through JTAG or Spy Bi Wire connectors The programming can be done with a PC or as a stand alone device A PC side graphical user interface is also available and is DLL based 7 4 Documentatio...

Page 69: ... JTAG access security fuse that is available on all MSP430 devices This document describes device access using both the standard 4 wire JTAG interface and the 2 wire JTAG interface which is also referred to as Spy Bi Wire SBW MSP430 Hardware Tools User s Guide This manual describes the hardware of the TI MSP FET430 Flash Emulation Tool FET The FET is the program development tool for the MSP430 ult...

Page 70: ...r the application Capacitive Touch Sensing MSP430 Slider and Wheel Tuning Guide This application report provides guidelines on how to tune capacitive touch sliders and wheels running on the MSP430 microcontrollers It identifies the hardware and software parameters as well as explains the steps used in tuning sliders and wheels The slider and wheel tuning is based on the APIs defined in the Capacit...

Page 71: ...2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices 7 7 Trademarks ...

Page 72: ...430G2203 Mechanical Packaging and Orderable Information Copyright 2011 2016 Texas Instruments Incorporated 8 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser ba...

Page 73: ...oHS CU NIPDAU Level 1 260C UNLIM 40 to 85 M430G2233 MSP430G2233IPW20 ACTIVE TSSOP PW 20 70 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2233 MSP430G2233IPW20R ACTIVE TSSOP PW 20 2000 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2233 MSP430G2233IPW28 ACTIVE TSSOP PW 28 50 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2233 MSP430G2233IPW28R ACTIVE TS...

Page 74: ...2333IPW28R ACTIVE TSSOP PW 28 2000 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2333 MSP430G2333IRHB32R ACTIVE VQFN RHB 32 3000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 MSP430 G2333 MSP430G2333IRHB32T ACTIVE VQFN RHB 32 250 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 MSP430 G2333 MSP430G2403IN20 ACTIVE PDIP N 20 20 Pb Free RoHS CU NIPDAU Level 1 26...

Page 75: ... 20 2000 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2533 MSP430G2533IPW28 ACTIVE TSSOP PW 28 50 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2533 MSP430G2533IPW28R ACTIVE TSSOP PW 28 2000 Green RoHS no Sb Br CU NIPDAU Level 1 260C UNLIM 40 to 85 430G2533 MSP430G2533IRHB32R ACTIVE VQFN RHB 32 3000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 MSP430 ...

Page 76: ... on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 6 Lead Ball Finish Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Inf...

Page 77: ... 16 0 Q1 MSP430G2233IPW28R TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 MSP430G2233IPW28R TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 MSP430G2233IRHB32R VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 1 8 0 12 0 Q2 MSP430G2233IRHB32T VQFN RHB 32 250 180 0 12 4 5 3 5 3 1 1 8 0 12 0 Q2 MSP430G2303IPW20R TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 Q1 MSP430G2303IPW28R TSSOP PW 28 2000 ...

Page 78: ...28R TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 MSP430G2433IRHB32R VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 1 8 0 12 0 Q2 MSP430G2433IRHB32T VQFN RHB 32 250 180 0 12 4 5 3 5 3 1 1 8 0 12 0 Q2 MSP430G2533IPW20R TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 Q1 MSP430G2533IPW28R TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 MSP430G2533IPW28R TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8...

Page 79: ... 250 210 0 185 0 35 0 MSP430G2333IPW20R TSSOP PW 20 2000 367 0 367 0 38 0 MSP430G2333IPW28R TSSOP PW 28 2000 367 0 367 0 38 0 MSP430G2333IRHB32R VQFN RHB 32 3000 367 0 367 0 35 0 MSP430G2333IRHB32T VQFN RHB 32 250 210 0 185 0 35 0 MSP430G2403IPW20R TSSOP PW 20 2000 367 0 367 0 38 0 MSP430G2403IPW28R TSSOP PW 28 2000 367 0 367 0 38 0 MSP430G2403IRHB32R VQFN RHB 32 3000 367 0 367 0 35 0 MSP430G2403I...

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Page 88: ...ATING PLANE 1 8 17 24 9 16 32 25 OPTIONAL PIN 1 ID 0 1 C A B 0 05 C EXPOSED THERMAL PAD 33 SYMM SYMM NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 The package thermal pad must be soldered to the printed circuit board for thermal and mechanical pe...

Page 89: ...ckage is designed to be soldered to a thermal pad on the board For more information see Texas Instruments literature number SLUA271 www ti com lit slua271 5 Vias are optional depending on application refer to device data sheet If any vias are implemented refer to their locations shown on this view It is recommended that vias under paste be filled plugged or tented 33 SOLDER MASK OPENING METAL UNDE...

Page 90: ...AD 4222893 A 04 2016 NOTES continued 6 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 33 SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 33 75 PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE 20X SYMM 1 8 9 16 17 24 25 32 ...

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Page 93: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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