PxDIR.y
From Timer
P1.0/TA0CLK/ ACLK/A0*
P1.1/TA0.0/
UCA0RXD/UCA0SOMI/A1*
P1.2/TA0.1/
UCA0TXD/UCA0SIMO/A2*
From USCI
1
* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.
To Module
From Timer
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxSEL2.y
1
0
INCHx = y *
ADC10AE0.y *
To ADC10 *
PxSEL.y
1
3
2
1
0
PxSEL2.y
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxSEL.y
3
2
1
0
PxSEL2.y
0
48
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
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MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
6.10 I/O Port Diagrams
6.10.1 Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
Figure 6-6
shows the port diagram.
Table 6-16
summarizes the selection of the pin functions.
Figure 6-6. Port P1 (P1.0 to P1.2) Diagram
