STE
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
STE,LEAD
1/f
UCxCLK
t
STE,LAG
t
STE,DIS
t
STE,ACC
t
HD,MO
t
LO/HI
t
LO/HI
STE
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
STE,LEAD
1/f
UCxCLK
t
LO/HI
t
LO/HI
t
STE,LAG
t
STE,DIS
t
STE,ACC
t
HD,SO
29
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
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Specifications
Copyright © 2011–2016, Texas Instruments Incorporated
5.27 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-18
and
Figure 5-19
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
t
STE,LEAD
STE lead time, STE low to clock
3 V
50
ns
t
STE,LAG
STE lag time, Last clock to STE high
3 V
10
ns
t
STE,ACC
STE access time, STE low to SOMI data out
3 V
50
ns
t
STE,DIS
STE disable time, STE high to SOMI high
impedance
3 V
50
ns
t
SU,SI
SIMO input data setup time
3 V
15
ns
t
HD,SI
SIMO input data hold time
3 V
10
ns
t
VALID,SO
SOMI output data valid time
UCLK edge to SOMI valid,
C
L
= 20 pF
3 V
50
75
ns
Figure 5-18. SPI Slave Mode, CKPH = 0
Figure 5-19. SPI Slave Mode, CKPH = 1
