Run-Time Interfaces/Integration Guide
I-A-13
3.2
Data Structures
This section summarizes the entire user visible data structure
elements pertaining to the
EDMA3 Driver
run-time interfaces.
3.2.1
EDMA3_DRV_GblConfigParams
This configuration structure is used to specify the EDMA3 Resource
Manager global settings, specific to the SoC. For e.g. number of
DMA/QDMA channels, number of PaRAM sets, TCCs, event queues,
transfer controllers, base addresses of CC global registers and TC
registers, interrupt number for EDMA3 transfer completion, CC
error, event queues’ priority, watermark threshold level etc.
This configuration information is SoC specific and could be provided
by the user at run-time while creating the EDMA3 Driver Object. In
case user doesn’t provide it, this information could be taken from
the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in
case it is available.
Member
Description
numDmaChannels
Number of DMA Channels supported by the underlying
EDMA3 Controller
numQdmaChannels
Number of QDMA Channels supported by the underlying
EDMA3 Controller
numTccs
Number of Interrupt Channels supported by the
underlying EDMA3 Controller
numPaRAMSets
Number of PaRAM Sets supported by the underlying
EDMA3 Controller
numEvtQueue
Number of Event Queues in the underlying EDMA3
Controller
numTcs
Number of Transfer Controllers (TCs) in the underlying
EDMA3 Controller
numRegions
Number of Regions in the underlying EDMA3 controller
dmaChPaRAMMapExists
Channel mapping existence:
A value of 0 (No channel mapping) implies that there is
fixed association between a DMA channel and a PaRAM
Set or, in other words, DMA channel n can ONLY use
PaRAM Set n (No availability of DCHMAP registers) for
transfers to happen.
A value of 1 implies the presence of DCHMAP registers
for the DMA channels and hence the flexibility of
associating any DMA channel to any PaRAM Set. In other
words, ANY PaRAM Set can be used for ANY DMA channel
(like QDMA Channels).
Summary of Contents for EDMA3
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Page 17: ...EDMA3 Driver Introduction I 1 5 ...
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Page 40: ...Run Time Interfaces Integration Guide A 12 EDMA3_DRV_IOCTL_MAX_IOCTL Max IOCTL ...
Page 75: ...Run Time Interfaces Integration Guide I A 47 Errors EDMA3_DRV_E_INVALID_PARAM ...
Page 107: ...Run Time Interfaces Integration Guide I A 79 ...