EDMA3 Driver Porting
A-92
{
16u,
16u,
16u,
0u,
0u,
0u,
0u,
0u
},
/**
* \brief To Configure the Default Burst Size (DBS) of TCs.
* An optimally-sized command is defined by the transfer controller
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
{
16u,
32u,
64u,
0u,
0u,
0u,
0u,
0u
},
/**
* \brief Mapping from each DMA channel to a Parameter RAM set,
* if it exists, otherwise of no use.
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
* \brief Mapping from each DMA channel to a TCC. This specific
* TCC code will be returned when the transfer is completed
* on the mapped channel.
*/
{
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 2u, 3u,
4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u,
12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u,
20u, 21u, 22u, 23u,
24u, 25u, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
28u, 29u, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
36u, 37u, 38u, 39u,
40u, 41u, 42u, 43u,
44u, 45u, 46u, EDMA3_DRV_CH_NO_TCC_MAP,
48u, 49u, 50u, 51u,
52u, 53u, 54u, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
},
Summary of Contents for EDMA3
Page 12: ......
Page 17: ...EDMA3 Driver Introduction I 1 5 ...
Page 20: ......
Page 40: ...Run Time Interfaces Integration Guide A 12 EDMA3_DRV_IOCTL_MAX_IOCTL Max IOCTL ...
Page 75: ...Run Time Interfaces Integration Guide I A 47 Errors EDMA3_DRV_E_INVALID_PARAM ...
Page 107: ...Run Time Interfaces Integration Guide I A 79 ...