Texas Instruments EDMA3 User Manual Download

Page: 80 / 131

Run-Time Interfaces/Integration Guide

A-52

3.3.3.20

EDMA3_DRV_getPaRAM ()

Prototype

EDMA3_DRV_Result EDMA3_DRV_getPaRAM (

EDMA3_DRV_Handle hEdma, unsigned int lCh, const

EDMA3_DRV_PaRAMRegs *currPaRAM);

Description

Retrieve existing PaRAM set associated with

specified logical channel (DMA/QDMA/Link).

<arg1>

hEdma

[IN] Handle to the EDMA3 Driver

Instance.

<arg2>

lCh

[IN]

Logical Channel for which new

PaRAM set is specified.

<arg3>

currPaRAM

[IN]

User gets the existing PaRAM

here.

Return value

EDMA3_DRV_SOK or EDMA3_DRV Error Code in

case of error.

Calling

constraints

Example

result = EDMA3_DRV_getPaRAM (hEdma, lCh,

&currPaRAM);

Comments

This function is re-entrant.

See Also

Errors

EDMA3_DRV_E_INVALID_PARAM

Summary of Contents for EDMA3

Page 1: ...November 2009 Anuj Aggarwal Document Version 01 11 00 XX EDMA3 Driver U s e r s G u i d e User Guide ...

Page 2: ...plied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information...

Page 3: ...river is Architected its composition its functionality the requirements it places on the hardware and software environment where it can be deployed how to customize configure it to specific requirements how to leverage the supported run time interfaces in user s own application etc This manual also provides supplementary information regarding steps to be followed for proper installation un install...

Page 4: ...ntroller EDMA3CC and EDMA3 transfer memory access controller s EDMA3TC Is referred to as EDMA3 in this document DMA Direct Memory Access QDMA Quick DMA TCC Transfer Completion Code basically Interrupt Channel ISR Interrupt Service Routine CC Channel Controller TC Transfer Controller RM Resource Manager TR Transfer Request A command for data movement that is issued from the EDMA3CC to the EDMA3TC A...

Page 5: ... and warnings CAUTION WARNING The information in a caution or a warning is provided for your protection Please read each caution and warning carefully This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation that could potentially c...

Page 6: ...A3 Channel Controller TPCC version 3 0 2 EDMA3 Transfer Controller TPTC version 3 0 1 Trademarks The TI logo design is a trademark of Texas Instruments Incorporated All other brand and product names may be trademarks of their respective companies ...

Page 7: ...wal a Added support for new platforms b IR SDOCM00049778 is fixed See release notes for more information 01 06 00 01 March 20 2008 Anuj Aggarwal a Added support for new platforms b MRs DPSP00010071 DPSP00010187 DPSP00010479 and DPSP00010480 are fixed See release notes for more information 1 05 00 01 January 28 2008 Anuj Aggarwal a Header files modified to have extern C declarations b Implemented E...

Page 8: ...false missed events Fixed 1 0 0 1 May 9 2007 Anuj Aggarwal a MR DPSP00007800 Result of resource allocation is over written by the semaphore release result in EDMA3 Resource Manager Fixed b MR DPSP00007803 Exit from EDMA3_RM_allocContiguousResource in case of error is incorrect Fixed 1 0 0 Apr 23 2007 Anuj Aggarwal a New APIs to support POLL mode provided b API to set CC Register provided c Sample ...

Page 9: ...evelopment Tools Environment s 1 2 4 2 2 1 Development Tools 1 2 4 2 3 Installation guide 1 2 5 2 3 1 Installation and Usage Procedure 1 2 5 2 3 2 Un installation 1 2 5 2 4 Integration Guide 1 2 6 2 4 1 Building EDMA3 Libraries 1 2 6 2 4 2 Building the EDMA3 Driver Stand alone Applications 1 2 6 2 4 3 Building the DAT Example 1 2 7 2 4 4 Build Options 1 2 8 Run Time Interfaces Integration Guide 2 ...

Page 10: ...MA3 Request Channel LINK Channel 2 A 75 3 5 5 EDMA3 Close 2 A 76 3 5 6 EDMA3 Delete 2 A 77 3 6 API Usage Example 2 A 78 EDMA3 Driver Porting 3 A 84 3 7 Getting Started 3 A 85 3 8 Step by Step procedure for porting 3 A 87 3 8 1 edma3_ PLATFORM_NAME _cfg c 3 A 87 3 8 2 edma3_rm_bios_ PLATFORM_NAME _lib pjt 3 A 88 3 8 3 OS dependent sample Implementation 3 A 89 ...

Page 11: ...onents 1 2 4 Table 2 Build Options 1 2 8 Table 3 Symbolic Constants and Enumerated Data types Table for common header file edma3_common h 2 A 2 Table 4 Symbolic Constants and Enumerated Data types Table for EDMA3 Driver header file edma3_drv h 2 A 4 ...

Page 12: ......

Page 13: ...tion This chapter introduces the EDMA3 Driver to the user by providing a brief overview of the purpose and construction of the EDMA3 Driver along with hardware and software environment specifics in the context of EDMA3 Driver Deployment ...

Page 14: ...applications for submitting and synchronizing with EDMA3 based DMA transfers In order to simplify the usage this component internally uses the services of the EDMA3 Resource Manager and provides one consistent interface for applications or device drivers The EDMA3 Resource Manager comprises of the following two parts Physical Driver This component is responsible for the management of several resou...

Page 15: ... EDMA3 Related Software Product and Packages Structure Dependency EDMA3 Resource Manager PaRAMs DMA QDMA Channels TCCs EDMA3 ISRs EDMA3 Driver Internally calls EDMA3 Product PSP Drivers CSL DAT Framework Components DMAN 3 ACPY 3 Applications ...

Page 16: ...in normal circumstances EDMA3 Driver doesn t allow multiple instances for a single master on the respective shadow region It permits only one instance for each master which will be tied to its specific shadow region This is done to prevent any potential problem which could arise due to EDMA3 resources conflict among these different instances However it is possible to have multiple EDMA3 Driver Ins...

Page 17: ...EDMA3 Driver Introduction I 1 5 ...

Page 18: ...OT mapped to a hardware sync event QDMA Channel and Link Channel a PARAM Set in EDMA3 1 1 2 2 Programs DMA channel It provides an interface that applications or device drivers can use to program a DMA transaction This typically involves setting the DMA source and destination parameters Following types of transactions are supported Event triggered peripheral driven transfers Chain triggered issuing...

Page 19: ...rocessor but manage same different set of EDMA3 resources and are tied to different shadow regions Please note that EDMA3 Driver doesn t allow multiple instances for a single master on the respective shadow region 1 1 2 7 Read Write a specific CC register It also provides an interface which enables users to read write any EDMA3 Channel Controller register These APIs are for advanced users and coul...

Page 20: ......

Page 21: ... Chapter 2 Installation Guide This chapter discusses the EDMA3 Driver installation how and what software and hardware components to be availed in order to complete a successful installation of EDMA3 Driver ...

Page 22: ...er Directory Structure The sections below describe the folder contents edma3_lld_ version_number Top level installation directory Contains the source code examples and the documents docs Contains release notes for EDMA3 Driver and Resource Manager examples Contains the stand alone applications for EDMA3 Driver for all the supported platforms and the DAT example ...

Page 23: ...re built libraries for the same o drv sample build Build files for CCSv3 CCSv4 eBinder o drv sample lib Pre built libraries for EDMA3 driver sample initialization code o drv sample src Source code for EDMA3 driver sample initialization f drv src Source files for EDMA3 Driver Just to clarify the sample folder inside the edma3 drv folder DOESNOT contain the sample applications It provides the Sample...

Page 24: ... tools that need to be installed the installation order and specific configuration Including 3rd party components libraries Operating system and auxiliary Tools Table 1 Development Tools components Development tool component Version Comments Code Composer Studio CCS 3 3 80 11 service release 10 IDE DSP BIOS 5 41 01 09 Operating System XDC tool chain 3 16 00 18 RTSC tools Code Generation Tools 6 1 ...

Page 25: ...ironment variable EDMA3LLD_BIOS5_INSTALLDIR is created with its value as the current EDMA3 installation directory Moreover in case the variable exists prior to this installation the same will be updated with the current latest EDMA3 installation directory This environment variable can be used by other users of EDMA3 package for e g BIOS PSP Drivers package 4 For building the downloadable images re...

Page 26: ...me folder needs to be imported via CCSv4 into a workspace to build the EDMA3 Driver libraries for the desired target C64P or C674X Similarly projects located in drv sample build platform_name ccs4 folder needs to be imported via CCSv4 into a workspace to build the EDMA3 Driver Sample Initialization libraries for the desired platform 2 4 2 Building the EDMA3 Driver Stand alone Applications The EDMA...

Page 27: ...ge contains CSL 2 0 DAT Adapter Reference Implementation using EDMA3 Low Level Driver The same can be built using the steps shown in the previous section The application can be located at edma3_lld_ version_number examples CSL2_DAT_DEMO demo in the platform specific folder ...

Page 28: ... Issues remarks non serious warnings which are suppressed by default o2 o2 Release Mode To choose O2 level of optimization Table 2 Build Options Note 1 All EDMA3 public APIs provide a mechanism to disable input parameter checking This is intended to reduce the number of CPU cycles spent in the parameter checking and hence provide more efficient libraries To do that user has to modify the build env...

Page 29: ... 3 Run Time Interfaces Integration Guide This chapter discusses the EDMA3 Driver run time interfaces that comprise the API specification usage scenarios in association with its data types and structure definitions ...

Page 30: ...O_TIMEOUT This define is used to specify a blocking call without timeout while requesting a semaphore EDMA3_MAX_ EDMA3_INSTANCES Maximum EDMA3 Controllers on the SoC EDMA3_MAX_DMA_CH Maximum DMA channels supported by the EDMA3 Controller EDMA3_MAX_QDMA_CH Maximum QDMA channels supported by the EDMA3 Controller EDMA3_MAX_PARAM_SETS Maximum PaRAM Sets supported by the EDMA3 Controller EDMA3_MAX_LOGI...

Page 31: ...EDMA3_MAX_TCC_DWRDS Maximum Words 4 bytes region required for the book keeping information specific to the maximum possible TCCs EDMA3_OS_PROTECT_INTERRUPT Protection from All Interrupts required EDMA3_OS_PROTECT_SCHEDULER Protection from scheduling required EDMA3_OS_PROTECT_INTERRUPT_XFER_ COMPLETION Protection from EDMA3 Transfer Completion Interrupt required EDMA3_OS_PROTECT_INTERRUPT_CC_E RROR...

Page 32: ...el requested for allocation is not available EDMA3_DRV_E_QDMA_CHANNEL_UNAVA IL QDMA channel requested for allocation is not available EDMA3_DRV_E_PARAM_SET_UNAVAIL PARAM Set requested for allocation is not available EDMA3_DRV_E_TCC_UNAVAIL TCC requested for allocation is not available EDMA3_DRV_E_TCC_REGISTER_FAIL Registration of the callback function against a specific TCC failed EDMA3_DRV_E_CH_P...

Page 33: ... should mandatorily be used to mark DMA channels with no initial mapping to a specific TCC EDMA3_DRV_DMA_CHANNEL_ANY Used to specify any available DMA Channel while requesting one It is used in the API EDMA3_DRV_requestChannel DMA channel from the pool of owned non_reserved available_right_now DMA channels will be chosen and returned EDMA3_DRV_QDMA_CHANNEL_ANY Used to specify any available QDMA Ch...

Page 34: ...channel EDMA3_DRV_QDMA_CHANNEL_6 QDMA Channel 6 define It used while requesting the specific QDMA channel EDMA3_DRV_QDMA_CHANNEL_7 QDMA Channel 7 define It used while requesting the specific QDMA channel Enum EDMA3_DRV_HW_C HANNEL_EVENT EDMA3_DRV_HW_CHANNEL_EVENT_0 0 EDMA3_DRV_HW_CHANNEL_EVENT_1 EDMA3_DRV_HW_CHANNEL_EVENT_2 DMA Channels assigned to different Hardware Events They should be used whi...

Page 35: ...ble disable Enum EDMA3_DRV_AddrMo de EDMA3_DRV_ADDR_MODE_INCR Increment INCR mode Source addressing within an array increments Source is not a FIFO EDMA3_DRV_ADDR_MODE_FIFO FIFO mode Source addressing within an array wraps around upon reaching FIFO width Enum EDMA3_DRV_SyncTyp e EDMA3_DRV_SYNC_A A synchronized Each array is submitted as one TR BCNT CCNT number of sync events are needed to complete...

Page 36: ...ansfer is considered completed after the data has been transferred EDMA3_DRV_TCCMODE_EARLY Early completion A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC TC may still be transferring data when interrupt chain is triggered Enum EDMA3_DRV_TcintEn EDMA3_DRV_TCINTEN_DIS Transfer complete interrupt is disabled EDMA3_DRV_TCINTEN_EN Transfer complete interrupt is enable...

Page 37: ... every intermediate chained transfer completion upon completion of every intermediate TR in the PaRAM set except the final TR in the PaRAM set The bit position set in CER or CERH is the TCC value specified Enum EDMA3_DRV_TrigMod e EDMA3_DRV_TRIG_MODE_MANUAL EDMA Trigger Mode Selection Set the Trigger mode to Manual The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the...

Page 38: ...SRCADDR PaRAM Set Field type Starting byte address of Source For FIFO mode srcAddr must be a 256 bit aligned address EDMA3_DRV_PARAM_FIELD_ACNT PaRAM Set Field type Number of bytes in each Array ACNT EDMA3_DRV_PARAM_FIELD_BCNT PaRAM Set Field type Number of Arrays in each Frame BCNT EDMA3_DRV_PARAM_FIELD_DESTADDR PaRAM Set Field type Starting byte address of destination For FIFO mode destAddr must...

Page 39: ...t be cleared during allocation depending upon this option For e g To clear the PaRAM Sets during allocation cmdArg void 1 To NOT clear the PaRAM Sets during allocation cmdArg void 0 For all other values it will return error By default PaRAM Sets will be cleared during allocation Note Since this enum can change the behavior how the resources are initialized during their allocation user is adviced t...

Page 40: ...Run Time Interfaces Integration Guide A 12 EDMA3_DRV_IOCTL_MAX_IOCTL Max IOCTL ...

Page 41: ...ailable Member Description numDmaChannels Number of DMA Channels supported by the underlying EDMA3 Controller numQdmaChannels Number of QDMA Channels supported by the underlying EDMA3 Controller numTccs Number of Interrupt Channels supported by the underlying EDMA3 Controller numPaRAMSets Number of PaRAM Sets supported by the underlying EDMA3 Controller numEvtQueue Number of Event Queues in the un...

Page 42: ...alue that is set in the queue watermark threshold register QWMTHRA tcDefaultBurstSize EDMA3 _MAX_TC To Configure the Default Burst Size DBS of TCs An optimally sized command is defined by the transfer controller default burst size DBS Different TCs can have different DBS values It is defined in Bytes dmaChannelPaRAMMap EDMA3_MAX_DMA_CH If channel mapping exists DCHMAP registers are present this ar...

Page 43: ...Integration Guide I A 15 DMA channels which are tied to some peripheral are RESERVED for that peripheral only They are not allocated when user asks for ANY DMA channel All channels need not be mapped some can be free also ...

Page 44: ...have catastrophic consequences Reserved resources During EDMA3 driver initialization user can reserve some of the EDMA3 resources for future use by specifying which resources to reserve in the configuration data structure These critical resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose User can request ...

Page 45: ...Driver Instance ownQdmaChannels EDMA3_MAX_QDMA_CHAN_DWRDS QDMA channels owned by the EDMA3 Driver Instance ownTccs EDMA3_MAX_TCC_DWRDS TCCs owned by the EDMA3 Driver Instance resvdPaRAMSets EDMA3_MAX_PARAM_DWRDS PaRAM Sets reserved during initialization for future use These will not be given when user requests for ANY available PaRAM Set using EDMA3_DRV_LINK_CHANNEL as resource channel id resvdDma...

Page 46: ...ces related shadow region specific information Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure User can also pass this structure as NULL In that case default static configuration would be taken from the platform specific configuration files part of the Resource Manager if available drvSemHandle Driver Instance specific semaphore...

Page 47: ...the Driver object New options may also be added into this structure in future Member Description isSlave In a multi master system for e g ARM DSP this option is used to distinguish between Master and Slave Only the Master is allowed to program the global EDMA3 registers like Queue priority Queue water mark level error registers etc param For future use ...

Page 48: ... TR in the PaRAM set The bit position set in CER or CERH is the TCC value specified tcintEn Transfer complete interrupt enable When enabled the interrupt pending register IPR IPRH bit is set on transfer completion upon completion of the final TR in the PaRAM set The bit position set in IPR or IPRH is the TCC value specified In order to generate a completion interrupt to the CPU the corresponding I...

Page 49: ...ration valid values for BCNT are between 1 and 65535 Therefore the maximum number of arrays in a frame is 65535 A BCNT equal to 0 is considered either a null or dummy transfer A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT destAddr The 32 bit destination address parameter specifies the starting byte address of the destination For ...

Page 50: ... appropriately For AB synchronized transfers BCNTRLD is not used srcCIdx SRCCIDX is a 16 bit signed value 2s complement used for source address modification in the 3rd dimension Valid values for SRCCIDX are between 32768 and 32767 It provides a byte address offset from the beginning of the current array pointed to by SRC address to the beginning of the first source array in the next frame It appli...

Page 51: ...2 7 EDMA3_DRV_EvtQuePriority This configuration structure is used to set the event queues priorities It allows to change the priority of the individual queues and the priority of the transfer request TR associated with the events queued in the queue ...

Page 52: ...Run Time Interfaces Integration Guide A 24 3 3 API Specification This section introduces the application programming interface API for the EDMA3 Driver ...

Page 53: ...e SoC specific configuration file edma3_ SOC_NAME _cfg c in case it is available This API clears all DCHMAP Registers in case they are present clears all PaRAM Sets clears the error specific registers EMCR EMCRh QEMCR CCERRCLR and sets the TCs priorities and Event Queues watermark levels After successful completion of this API Driver Object s state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELET...

Page 54: ...event queues transfer controllers base addresses of CC global registers and TC registers interrupt number for EDMA3 transfer completion CC error event queues priority watermark threshold level etc This configuration information is EDMA3 hardware specific and should be provided by the user while creating the EDMA3 Driver object Side effects See Also Errors EDMA3_DRV_E_INVALID_PARAM EDMA3_DRV_E_OBJ_...

Page 55: ...NE Master Driver Instance is permitted This master instance and hence the region to which it belongs will only receive the EDMA3 interrupts if enabled User could pass the instance specific configuration structure initCfg drvInstInitConfig as a part of the initCfg structure during init time In case user doesn t provide it this information could be taken from the SoC specific configuration file edma...

Page 56: ... this region and resources reserved by this region drvSemHandle Instance specific semaphore handle Used to share resources DMA QDMA channels PaRAM Sets TCCs etc among different users Provided by the user gblerrCb Instance wide global callback function to catch non channel specific errors from the EDMA3 Channel Controller for e g TCC error queue threshold exceed error etc gblerrData Application dat...

Page 57: ...ent queue 1 arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 pLch IN OUT Requested logical channel number arg3 pTcc IN OUT The channel number on which the completion error interrupt is generated arg4 evtQueue IN Event Queue Number to which the channel will be mapped valid only for the Master Channel request Arguments arg5 tccCb IN TCC callback caters to channel specific events like Event Mis...

Page 58: ...aster EDMA3 Channel To request a PaRAM Set for the purpose of linking use this b Channel number on which the completion interrupt error will be generated could be 1 EDMA3_DRV_HW_CHANNEL_EVENT_0 TCC associated with DMA Channel mapped to EDMA3 Event 0 2 EDMA3_DRV_TCC_ANY Any TCC with no event mapping c This API will not enable the interrupts IER IERH register if the callback function specified by th...

Page 59: ... hEdma IN Handle to the EDMA3 Driver Instance Argument s arg2 channelId IN Logical Channel number to be freed Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_freeChannel hEdma chId Comments This function disables the global interrupts while modifying the global CC registers and while modifying global data structures to prevent simult...

Page 60: ...el and brings back EDMA3 to its initial state arg1 hEdma IN Handle to the EDMA3 Driver Instance Argument s arg2 channelId IN Logical Channel number to be cleaned Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_clearErrorBits hEdma chId Comments This function is re entrant for unique channelId values It is non re entrant for same chan...

Page 61: ...e channel arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh1 IN Logical Channel to which particular channel will be linked Arguments arg3 lCh2 IN Logical Channel which needs to be linked to the first channel After the transfer based on the PaRAM set of lCh1 is over the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume For DMA channels another sync event is...

Page 62: ...cified channel and the earlier linked logical channel by clearing the Link Address field arg1 hEdma IN Handle to the EDMA3 Driver Instance Argument s arg2 lCh IN Channel for which linking has to be removed Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_unlinkChannel hEdma chId Comments This function is re entrant for unique lCh valu...

Page 63: ...enable disable chaining setting the transfer mode A AB Sync setting the FIFO width etc arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel bound to which PaRAM set OPT field needs to be set Arguments arg3 optField IN The particular field of OPT Word that needs setting arg4 newOptFieldVal IN The new OPT field value Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case...

Page 64: ...sable completion interrupts enable disable chaining setting the transfer mode A AB Sync setting the FIFO width etc arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel bound to which PaRAM Set OPT field is required Arguments arg3 optField IN The particular field of OPT Word that is needed arg4 optFieldVal IN OUT Value of the OPT field Return value EDMA3_DRV_SOK or EDMA3_DR...

Page 65: ...st be 32 bytes aligned arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel for which the source parameters need to be configured Arguments arg3 srcAddr IN Source address arg4 addrMode IN Address mode FIFO or Increment arg5 fifoWidth IN Width of FIFO Valid only if addrMode is FIFO EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDM...

Page 66: ...e 32 bytes aligned arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel for which the destination parameters are to be configured Arguments arg3 destAddr IN Destination address arg4 addrMode IN Address mode FIFO or Increment arg5 fifoWidth IN Width of FIFO Valid only if addrMode is FIFO Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints...

Page 67: ...es for SRCCIDX are between 32768 and 32767 It provides a byte address offset from the beginning of the current array pointed to by SRC address to the beginning of the first source array in the next frame It applies to both A synchronized and AB synchronized transfers Note that when SRCCIDX is applied the current array in an A synchronized transfer is the last array in the frame while the current a...

Page 68: ... 3rd dimension Valid values are between 32768 and 32767 It provides a byte address offset from the beginning of the current array pointed to by DST address to the beginning of the first destination array TR in the next frame It applies to both A synchronized and AB synchronized transfers Note that when DSTCIDX is applied the current array in an A synchronized transfer is the last array in the fram...

Page 69: ...er Controller An ACNT equal to 0 is considered either a null or dummy transfer A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT arg4 bCnt IN Count for 2nd Dimension BCNT is a 16 bit unsigned value that specifies the number of arrays of length ACNT For normal operation valid values for BCNT are between 1 and 65535 Therefore the maxim...

Page 70: ...CNTRLD is not used arg7 syncType IN Transfer synchronization dimension 0 A synchronized Each event triggers the transfer of a single array of ACNT bytes 1 AB synchronized Each event triggers the transfer of BCNT arrays of ACNT bytes Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_setTransferParams hEdma chId acnt bcnt ccnt BRCnt EDMA...

Page 71: ...be chained Arguments arg3 lCh2 IN Channel which needs to be chained to the first channel arg4 chainOptions IN Options such as intermediate final interrupts are required or not intermediate final chaining is enabled or not etc Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_chainChannel hEdma ch1Id ch2Id chainOpt Comments a The channe...

Page 72: ...Run Time Interfaces Integration Guide A 44 values It is non re entrant for same lCh1 lCh2 values See Also Errors EDMA3_DRV_E_INVALID_PARAM ...

Page 73: ...rg1 hEdma IN Handle to the EDMA3 Driver Instance Arguments arg2 lCh IN Channel whose chaining with the other channel has to be removed Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_unchainChannel hEdma chId Comments This function is re entrant for unique lCh values It is non re entrant for same lCh values See Also Errors EDMA3_DRV_...

Page 74: ...ent Set Register ESR ESRH This API writes to the ESR ESRH to start the transfer In QDMA triggered mode a QDMA transfer is triggered when a CPU or other EDMA3 programmer writes to the trigger word of the QDMA channel PaRAM set auto triggered or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel link triggered This API enables the QDMA channel by writing to...

Page 75: ...Run Time Interfaces Integration Guide I A 47 Errors EDMA3_DRV_E_INVALID_PARAM ...

Page 76: ...ich was previously triggered in QDMA mode this API clears the QDMA Even Enable Register for the specific QDMA channel To disable a channel which was previously triggered in event mode this API clears the Event Enable Register Event Register Secondary Event Register and Event Miss Register if set for the specific DMA channel arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Channel on w...

Page 77: ...r This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory to memory copy based transfers In case of that this API returns error arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN DMA QDMA Channel which needs to be disabled Arguments arg3 trigMode IN Mode of triggering start of transfer Return value EDMA3_DRV_SOK or EDMA3_DRV Error...

Page 78: ... Handle to the EDMA3 Driver Instance arg2 channelId IN QDMA Channel which needs to be assigned the Trigger Word Arguments arg3 trigWord IN The Trigger Word for the QDMA channel Trigger Word is the word in the PaRAM Register Set which when written to by CPU will start the QDMA transfer automatically Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example resu...

Page 79: ...AM Set is written first and the CCNT field is written last Caution It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel for which new PaRAM set is specified Arguments arg3 newPaRAM IN Parameter RAM set to be copied onto existing PaRAM Return value EDMA3_DRV_SOK or EDMA3_DR...

Page 80: ...d with specified logical channel DMA QDMA Link arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel for which new PaRAM set is specified Arguments arg3 currPaRAM IN User gets the existing PaRAM here Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_getPaRAM hEdma lCh currPaRAM Comments This function is re entra...

Page 81: ...ce arg2 lCh IN Logical Channel bound to the Parameter RAM set whose specified field needs to be set Arguments arg3 paRAMEntry IN Specify the PaRAM set entry which needs to be set arg4 newPaRAMEntryVal IN The new field setting Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_setPaRAMEntry hEdma qChId EDMA3_DRV_PARAM_ENTRY_DST unsigned ...

Page 82: ...IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel bound to the Parameter RAM set whose specified field needs to be get Arguments arg3 paRAMEntry IN Specify the PaRAM set entry which needs to be get arg4 paRAMEntryVal IN The value of the field Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_getPaRAMEntry hEdma qChId E...

Page 83: ...nce arg2 lCh IN Logical Channel bound to the Parameter RAM set whose specified field needs to be set Arguments arg3 paRAMField IN Specify the PaRAM set field which needs to be set arg4 newPaRAMFieldVal IN The new field setting Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_setPaRAMField hEdma lCh EDMA3_DRV_PARAM_FIELD_SRCADDR newPaR...

Page 84: ...dle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel bound to the Parameter RAM set whose specified field needs to be get Arguments arg3 paRAMField IN Specify the PaRAM set field which needs to be get arg4 currPaRAMFieldVal IN The value of the field Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_getPaRAMField hEdma lCh EDMA3...

Page 85: ...of an IO initiated by either of the TCs Transfer Controllers relative to IO initiated by the other bus masters on the device ARM DSP USB etc arg1 hEdma IN Handle to the EDMA3 Driver Instance Argume nts arg2 evtQPriObj IN Priority of the Event Queues Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_setEvtQPriority hEdma evtQPriObj Comm...

Page 86: ...river Instance arg2 channelId IN Logical Channel to which the Event Queue is to be mapped Arguments arg3 eventQ IN The Event Queue which is to be mapped to the DMA channel Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_mapChToEvtQ hEdma channelId eventQ Comments This function disables the global interrupts while modifying the global...

Page 87: ...A QDMA channel arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 channelId IN Logical Channel whose associated Event Queue is needed Arguments arg3 mappedEvtQ IN OUT The Event Queue which is mapped to the DMA QDMA channel Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_getMapChToEvtQ hEdma channelId mappedEvtQ Comments This func...

Page 88: ...ue needs to be set Arguments arg3 newRegValue IN New CC Register Value Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_setCCRegister hEdma ccRegOffset newRegVal Comments This function is non re entrant for users using the same EDMA handle i e working on the same shadow region Before modifying a register it tries to acquire a semaphor...

Page 89: ...nce all the CC registers are 4 bytes in length the offset specified should be 4 bytes aligned in nature arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 regOffset IN CC Register offset whose value is needed Arguments arg3 regValue IN OUT CC Register Value Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_getCCRegister hEdma ccReg...

Page 90: ...It clears the corresponding bit while returning also arg1 hEdma IN Handle to the EDMA3 Driver Instance Arguments arg2 tccNo IN TCC specific to which the function waits on a IPR IPRH bit Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_waitAndClearTcc hEdma tccNo Comments This function is re entrant for different tccNo THIS FUNCTION WA...

Page 91: ...rresponding bit if SET while returning also arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 tccNo IN TCC specific to which the function checks the status of the IPR IPRH bit Arguments arg3 tccStatus IN OUT Status of the transfer is returned here Returns TRUE if the transfer has completed IPR IPRH bit SET FALSE if the transfer has not completed successfully IPR IPRH bit NOT SET Return value ...

Page 92: ...be performed Arguments arg3 cmdArg IN OUT IOCTL command argument if any arg4 param IN OUT Device Cmd specific argument Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_Ioctl hEdma EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION void 1 NULL Comments For EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION this function is re entrant For EDMA3_DRV_IOCTL_SET_P...

Page 93: ...ld be used to program the LINK field in the PaRAM Set Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel arg1 hEdma IN Handle to the EDMA3 Driver Instance arg2 lCh IN Logical Channel for which the PaRAM set offset is required Arguments arg3 paramPhyAddr IN OUT PaRAM Set Offset Value Return value EDMA3_DRV_SOK or EDMA3_DRV E...

Page 94: ...alue whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode arg1 phyCtrllerInstId IN EDMA3 Controller Instance Id Hardware instance id starting from 0 arg2 regionId IN Shadow Region id for which the previously opened driver s instance handle is required Arguments arg3 errorCode IN OUT Error code while returning Driver Instance Handle Return value EDMA3_DRV_Handle If successful this API w...

Page 95: ...Run Time Interfaces Integration Guide I A 67 b This function is re entrant See Also Errors EDMA3_DRV_E_INVALID_PARAM EDMA3_DRV_E_INST_NOT_OPENED ...

Page 96: ...Run Time Interfaces Integration Guide A 68 3 3 4 Termination This section should list all the EDMA3 Driver APIs that help in gracefully terminating the deployed EDMA3 Driver run time entities ...

Page 97: ...ty is no more required arg1 hEdma IN Handle to the EDMA3 Driver Instance Argume nts arg2 param IN For possible future use Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_close hEdma NULL Comments This function disables the global interrupts while modifying the global Driver data structures to make it re entrant See Also Errors EDMA3_...

Page 98: ... hardware instance Note It should be called ONLY after closing all the EDMA3 Driver Instances arg1 phyCtrllerInstId IN EDMA3 Controller Instance Id Hardware Instance Id starting from 0 Argument s arg2 param IN For possible future use Return value EDMA3_DRV_SOK or EDMA3_DRV Error Code in case of error Calling constraints Example result EDMA3_DRV_delete phyCtrllerInstId NULL Side effects See Also Er...

Page 99: ...ization routine or by the user itself for EDMA3 driver functioning Also they can be called further for other usage Note 1 During the initialization sequence EDMA3 Driver being an OS independent module doesn t register various interrupt handlers with the underlying OS The application which is using the EDMA3 Driver should register the various Interrupt Handlers ISRs in Resource Manager with the und...

Page 100: ...Run Time Interfaces Integration Guide A 72 3 5 API Flow Diagram Below are the flow diagrams for some EDMA3 Driver APIs which interact with the EDMA3 Resource Manager for their functioning ...

Page 101: ...source Manager HW EDMA3_DRV_create EDMA3_RM_create Reset all global info for this EDMA3 instance For each EDMA3 instance edma3GloablRegionInit Program H W Registers App Driver EDMA3 Driver EDMA3 Resource Manager HW EDMA3_DRV_open EDMA3_RM_open edma3ShadowRegionInit If required Program H W Registers For each EDMA3 instance ...

Page 102: ...ource Manager EDMA3_RM_allocResource EDMA3_RM_allocResource Allocate a PaRAM Set EDMA3_RM_registerTccCb Allocate a TCC Registers the TCC callback and Enable Interrupts if callback is not NULL Bind DMA QDMA channel to PARAM Set EDMA3_RM_mapEdmaChannel EDMA3_RM_mapQdmaChannel Make the LINK field of PaRAM Set NULL For QDMA Channel Enable the Transfer Associate Channel to Event Queue Bind PaRAM Set an...

Page 103: ...ation Guide I A 75 3 5 4 EDMA3 Request Channel LINK Channel App HW EDMA3_DRV_requestChannel Program Registers EDMA3 Driver EDMA3 Resource Manager EDMA3_RM_allocResource Allocate a PaRAM Set Make the LINK field of PaRAM Set NULL ...

Page 104: ...5 5 EDMA3 Close App Driver EDMA3 Driver EDMA3 Resource Manager HW EDMA3_DRV_close EDMA3_RM_close Set Driver s state as EDMA3_DRV_CLOSED If no other Driver Instance is there For each EDMA3 instance Set the RM Instance specific configuration as NULL ...

Page 105: ...App Driver EDMA3 Driver EDMA3 Resource Manager HW EDMA3_DRV_delete EDMA3_RM_delete Set Driver s state as EDMA3_DRV_DELETED If no other Driver Instance is there For each EDMA3 instance Set Resource Manager s state as EDMA3_RM_DELETED if no other RM Instance is there ...

Page 106: ...he steps required to create the Driver Object and then initialize a region specific Driver Instance Afterwards if required the application has to register the various interrupt handlers with the underlying OS After the successful opening the Driver instance can be used to call other EDMA3 Driver APIs ...

Page 107: ...Run Time Interfaces Integration Guide I A 79 ...

Page 108: ...L if NULL hEdma configuration structure for the Driver initCfg isMaster TRUE initCfg regionId EDMA3_RM_RegionId 1u initCfg drvSemHandle NULL Driver instance specific config NULL initCfg drvInstInitConfig NULL initCfg gblerrCb NULL initCfg gblerrData NULL Create EDMA3 Driver Object first edma3Result EDMA3_DRV_create edma3InstanceId NULL NULL if edma3Result EDMA3_DRV_SOK Report error return edma3Res...

Page 109: ...egration Guide I A 81 else Register Interrupt Handlers for various interrupts like transfer completion interrupt CC error interrupt TC error interrupts etc if required else EDMA3 Driver Already Initialized return edma3Result ...

Page 110: ...ic call back function along with the status code HW EDMA3_DRV_requestChannel EDMA3_DRV_freeChannel EDMA3 Driver EDMA3 Resource Manager App EDMA3_DRV_setTransferParams EDMA3_DRV_setSrcParams EDMA3_DRV_setDestParams EDMA3_DRV_setDestIndex EDMA3_DRV_setOptField EDMA3_DRV_enableTransfer EDMA3_DRV_setSrcIndex Call Resource Manager APIs Program Registers edma3ComplHandler tccCb Application specific call...

Page 111: ...EDMA3_DRV_SOK Un register Interrupt Handlers first if previously registered Delete the semaphore edma3Result edma3OsSemDelete semHandle if EDMA3_DRV_SOK edma3Result Report error return edma3Result else Make the semaphore handle as NULL semHandle NULL Now close the EDMA3 Driver Instance edma3Result EDMA3_DRV_close hEdma NULL if EDMA3_DRV_SOK edma3Result Report error return edma3Result else Now dele...

Page 112: ...EDMA3 Driver Porting A 84 Chapter 4 EDMA3 Driver Porting This chapter discusses how to port EDMA3 Driver and EDMA3 Resource Manager to other supported target platforms and operating systems ...

Page 113: ...which will take this configuration file as input and generate a platform specific library Support is already provided for multiple platforms To port to a new platform user is advised to look the existing files Also the EDMA3 Driver module is completely OS agnostic for make it s porting to a different OS completely hassle free It is designed in such a way that the OS dependent part has to be provid...

Page 114: ...nd un registration It is not done by the EDMA3 Driver or the Resource Manager The application which is using the EDMA3 Driver should register the various Interrupt Handlers ISRs in Resource Manager with the underlying OS on which it is running Similarly the application should un register the previously registered Interrupt Handlers when the Driver instance is no more required Public header file ed...

Page 115: ...available for the specific SoC Similarly EDMA3_DRV_InstanceInitConfig is the initialization structure which is used to specify the EDMA3 Resource Manager Region specific settings For e g resources DMA QDMA channels PaRAM sets TCCs owned and reserved by this EDMA3 driver instance This configuration information is shadow region or master specific and could be provided by the user at run time while c...

Page 116: ... the platform specific CCS PJT file This CCS PJT file will then generate the platform specific Resource Manager library User can find the various CCS PJT files for different platforms at edma3_lld_ VERSION_NUMBER packages ti sdo edma3 rm buil d in the platform specific folder On the same lines user can create different PJT file for another platform ...

Page 117: ...3_ERROR_INT 0u define EDMA3_TC4_ERROR_INT 0u define EDMA3_TC5_ERROR_INT 0u define EDMA3_TC6_ERROR_INT 0u define EDMA3_TC7_ERROR_INT 0u EDMA3 interrupts transfer completion CC error etc correspond to different ECM events SoC specific These ECM events come under ECM block XXX handling those specific ECM events Normally block 0 handles events 4 31 events 0 3 are reserved block 1 handles events 32 63 ...

Page 118: ...ed internally for referring transfer completion interrupt unsigned int ccXferCompInt EDMA3_CC_XFER_COMPLETION_INT Variable which will be used internally for referring channel controller s error interrupt unsigned int ccErrorInt EDMA3_CC_ERROR_INT Variable which will be used internally for referring transfer controllers error interrupts unsigned int tcErrorInt 8 EDMA3_TC0_ERROR_INT EDMA3_TC1_ERROR_...

Page 119: ...rror EDMA3_CC_ERROR_INT Interrupt no for TCs Error EDMA3_TC0_ERROR_INT EDMA3_TC1_ERROR_INT EDMA3_TC2_ERROR_INT EDMA3_TC3_ERROR_INT EDMA3_TC4_ERROR_INT EDMA3_TC5_ERROR_INT EDMA3_TC6_ERROR_INT EDMA3_TC7_ERROR_INT brief EDMA3 TC priority setting User can program the priority of the Event Queues at a system wide level This means that the user can set the priority of an IO initiated by either of the TC...

Page 120: ... 59u 60u 61u 62u 63u brief Mapping from each DMA channel to a TCC This specific TCC code will be returned when the transfer is completed on the mapped channel EDMA3_DRV_CH_NO_TCC_MAP EDMA3_DRV_CH_NO_TCC_MAP 2u 3u 4u 5u 6u 7u 8u 9u 10u 11u 12u 13u 14u 15u 16u 17u 18u 19u 20u 21u 22u 23u 24u 25u EDMA3_DRV_CH_NO_TCC_MAP EDMA3_DRV_CH_NO_TCC_MAP 28u 29u EDMA3_DRV_CH_NO_TCC_MAP EDMA3_DRV_CH_NO_TCC_MAP E...

Page 121: ... 0xFFFFFFFFu 0xFFFFFFFFu 0x00000FFFu 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u ownDmaChannels 0xFFFFFFFFu 0xFFFFFFF0u ownQdmaChannels 0x00000080u ownTccs 0xFFFFFFFFu 0xFFFFFFF0u Resources reserved by Region 1 resvdPaRAMSets EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u 0x0u resvdDmaC...

Page 122: ...s define is for the MAXIMUM size and hence the maximum data which could be transferred using the sample test cases below define MAX_BUFFER_SIZE 512u 32u 8u Cache line size on the underlying SoC It needs to be modified for different cache line sizes if the Cache is Enabled define EDMA3_CACHE_LINE_SIZE_IN_BYTES 128u To enable disable the cache define EDMA3_ENABLE_DCACHE 1u OPT Field specific defines...

Page 123: ...t void brief EDMA3 De initialization This function removes the EDMA3 RM Instance and unregisters the interrupt handlers It also deletes the RM Object return EDMA3_DRV_SOK if success else error code EDMA3_DRV_Result edma3deinit void brief EDMA3 Cache Invalidate This function invalidates the D cache param mem_start_ptr IN Starting adress of memory Please note that this should be aligned according to...

Page 124: ...ting semaphore with specified attributes and initial value It should be used to create a semaphore with initial value as 1 The semaphore is then passed by the user to the EDMA3 driver RM for proper sharing of resources param initVal IN is initial value for semaphore param attrs IN is the semaphore attributes ex Fifo type param hSem OUT is location to recieve the handle to just created semaphore re...

Page 125: ...y int level unsigned int intState if level EDMA3_OS_PROTECT_INTERRUPT level EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR intState NULL return else switch level case EDMA3_OS_PROTECT_INTERRUPT intState HWI_disable break case EDMA3_OS_PROTECT_SCHEDULER TSK_disable break case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION ECM_disableEvent ccXferCompInt break case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR ECM_disableEve...

Page 126: ...COMPLETION ECM_enableEvent ccXferCompInt break case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR ECM_enableEvent ccErrorInt break case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR switch intState case 0 case 1 case 2 case 3 case 4 case 5 case 6 case 7 ECM_enableEvent tcErrorInt intState break default break break default break Function to wait for OS Ticks void edma3OsWaitMsecs unsigned int mSecs unsigned int ticksF...

Page 127: ... EDMA3_NON_ALIGNED_BUFFERS_ERROR else BCACHE_inv void mem_start_ptr num_bytes EDMA3_CACHE_WAIT return cacheInvResult brief EDMA3 Cache Flush This function flushes cleans the Cache param mem_start_ptr IN Starting adress of memory Please note that this should be aligned according to the cache line size param num_bytes IN length of buffer return EDMA3_DRV_SOK if success else error code in case of err...

Page 128: ... attrs EDMA3_OS_Sem_Handle hSem EDMA3_DRV_Result semCreateResult EDMA3_DRV_SOK if NULL hSem semCreateResult EDMA3_DRV_E_INVALID_PARAM else hSem EDMA3_OS_Sem_Handle SEM_create initVal SEM_Attrs attrs if hSem NULL semCreateResult EDMA3_DRV_E_SEMAPHORE return semCreateResult Function to delete OS Semaphore EDMA3_DRV_Result edma3OsSemDelete EDMA3_OS_Sem_Handle hSem EDMA3_DRV_Result semDeleteResult EDM...

Page 129: ...A3_DRV_E_INVALID_PARAM else if TSK_self TSK_Handle KNL_dummy semPendResult SEM_pend hSem mSecTimeout if semPendResult FALSE semTakeResult EDMA3_DRV_E_SEMAPHORE return semTakeResult Function to give OS Semaphore EDMA3_DRV_Result edma3OsSemGive EDMA3_OS_Sem_Handle hSem EDMA3_DRV_Result semGiveResult EDMA3_DRV_SOK if NULL hSem semGiveResult EDMA3_DRV_E_INVALID_PARAM else if TSK_self TSK_Handle KNL_du...

Page 130: ...l TC error ISRs need to be registered register only for the available Transfer Controllers void ptrEdma3TcIsrHandler EDMA3_MAX_TC unsigned int arg lisrEdma3TC0ErrHandler0 lisrEdma3TC1ErrHandler0 lisrEdma3TC2ErrHandler0 lisrEdma3TC3ErrHandler0 lisrEdma3TC4ErrHandler0 lisrEdma3TC5ErrHandler0 lisrEdma3TC6ErrHandler0 lisrEdma3TC7ErrHandler0 To Register the ISRs with the underlying OS if required stati...

Page 131: ...ion number XXX is mapped to a specific HWI_INT YYY in the tcf file So to enable this mapped HWI_INT YYY one should use the corresponding bitmask in the API C64_enableIER in which the YYY bit is SET C64_enableIER EDMA3_HWI_BITMASK Restore interrupts HWI_restore intState To Unregister the ISRs with the underlying OS if previously registered static void unregisterEdma3Interrupts void unsigned int int...

Search results

Summary of Contents for EDMA3

Reviews:

Related manuals for EDMA3

Brands by name

Popular brands

Texas Instruments EDMA3, User Manual

Search results

Summary of Contents for EDMA3

Reviews:

Related manuals for EDMA3

Brands by name

Popular brands