DAC1006/1007/1008 — Simple
Hookup for a “Quick Look”
(Continued)
on how the 2nd digital data buffer (the DAC Latch) is up-
dated by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the µP and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logic. Further, the data
format can be either left justified or right justified.
When interfacing to a µP with a 16-bit data bus only two se-
lections are available: 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or 2)
operating with a double digital data buffer for simultaneous
transfer, or updating, of more than one DAC.
For operating without a µP in the stand alone mode, three
options are provided: 1) using only a single digital data
buffer, 2) using both digital data buffers — “double buff-
ered,” or 3) allowing the input digital data to “flow through” to
provide the analog output without the use of any data
latches.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
6.1 Interfacing to an 8-Bit Data Bus
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:
1.
Is the data to be left justified (considered as fractional bi-
nary data with the binary point to the left) or right justified
(considered as binary weighted data with the binary
point to the right)?
2.
Which byte will be transfered first, the most significant
byte (MS byte) or the least significant byte (LS byte)?
TABLE 1.
Operating Mode
Automatic Transfer
µP Control Transfer
External Transfer
Section
Figure No.
Section
Figure No.
Section
Figure No.
Data Bus
8-Bit Data Bus (6.1.0)
Left Justified (6.1.1)
6.2.1
16
6.2.2
16
6.2.3
16
16-Bit Data Bus (6.3.0)
Single Buffered
Double Buffered
Flow Through
6.3.1
17
6.3.2
17
Not Applicable
Stand Alone (6.4.0)
Single Buffered
Double Buffered
Flow Through
6.4.1
17
6.4.2
17
NA
These data possibilities are shown in
Figure 15. Note that
the justification of data depends on how the 10-bit data word
is located within the 16-bit data source (CPU) register. In ei-
ther case, there is a surplus of 6 bits and these are shown as
“don’t care” terms (“x”) in this figure.
All of these DACs load 10 bits on the 1st write cycle. A par-
ticular set of 2 bits is then overwritten on the 2nd write cycle,
depending on the justification of the data. For all left justified
data options, the 1st write cycle must contain the MS or Hi
Byte data group.
6.1.1 For Left Justified Data
For
applications
which
require
left
justified
data,
DAC1006–1008 can be used. A simplified logic diagram
which shows the external connections to the data bus and
the internal functions of both of the data buffer registers (In-
put Latch and DAC Register) is shown in
Figure 16. These
parts require the MS or Hi Byte data group to be transferred
on the 1st write cycle.
6.2 Controlling Data Transfer for an 8-Bit Data Bus
Three operating modes are possible for controlling the trans-
fer of data from the Input Latch to the DAC Register, where
it will update the analog output voltage. The simplest is the
automatic transfer mode, which causes the data transfer to
occur at the time of the 2nd write cycle. This is recom-
mended when the exact timing of the changes of the DAC
analog output are not critical. This typically happens where
each DAC is operating individually in a system and the ana-
log updating of one DAC is not required to be synchronized
to any other DAC. For synchronized DAC updating, two op-
tions are provided: µP control via a common XFER strobe or
external update timing control via an external strobe. The de-
tails of these options are now shown.
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PrintDate=1998/11/17 PrintTime=11:38:10 46711 ds005688 Rev. No. 4
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