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Electrical Characteristics

(Continued)

Note 10: A 200 nA leakage current with R

fb

=20K and V

REF

=10V corresponds to a zero error of (200x10

−9

x20x10

3

)x100÷10 which is 0.04% of FS.

Note 11: Human body model, 100 pF discharged through a 1.5 k

Ω

resistor.

Switching Waveforms

DS005688-2

www.national.com

4

PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4

cmserv

Proof

4

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Summary of Contents for DAC1006

Page 1: ...DAC1006 DAC1007 DAC1008 DAC1006 DAC1007 DAC1008 P Compatible Double Buffered D to A Converters Literature Number SNAS540 ...

Page 2: ...lutions the DAC0830 series 8 bits and the DAC1208 and DAC1230 12 bits are avail able alternatives Part Accuracy Pin Description bits DAC1006 10 For left DAC1007 9 20 justified DAC1008 8 data Features n Uses easy to adjust END POINT specs NOT BEST STRAIGHT LINE FIT n Low power consumption n Direct interface to all popular microprocessors n Integrated thin film on CMOS structure n Double buffered si...

Page 3: ... See Note VCC 12VDC 5 VCC 5VDC 5 to 15VDC 5 Units Min Typ Max Min Typ Max Resolution 10 10 bits Linearity Error Endpoint adjust only 4 7 TMIN TA TMAX 6 10V VREF 10V 5 DAC1006 0 05 0 05 of FSR DAC1007 0 1 0 1 of FSR DAC1008 0 2 0 2 of FSR Differential Endpoint adjust only 4 7 Nonlinearity TMIN TA TMAX 6 10V VREF 10V 5 DAC1006 0 1 0 1 of FSR DAC1007 0 2 0 2 of FSR DAC1008 0 4 0 4 of FSR Monotonicity...

Page 4: ...ified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part and the fact that there is no way to significantly modify the power dissipation removes concern for heat sinking Note 4 For current switching applications both IOUT1 and IOUT2 must go to...

Page 5: ...nd VREF 10V corresponds to a zero error of 200x10 9 x20x103 x100 10 which is 0 04 of FS Note 11 Human body model 100 pF discharged through a 1 5 kΩ resistor Switching Waveforms DS005688 2 www national com 4 PrintDate 1998 11 17 PrintTime 11 38 08 46711 ds005688 Rev No 4 cmserv Proof 4 ...

Page 6: ...Width tw DS005688 31 Control Setup Time tCS DS005688 32 Data Setup Time tDS DS005688 33 Data Hold Time tDH DS005688 34 Digital Threshold vs Supply Voltage DS005688 35 Digital Input Threshold vs Temperature DS005688 36 www national com 5 PrintDate 1998 11 17 PrintTime 11 38 08 46711 ds005688 Rev No 4 cmserv Proof 5 ...

Page 7: ...arts DS005688 5 Use DAC1006 1007 1008 for left justified data DAC1006 1007 1008 20 Pin Parts Dual In Line Package DS005688 28 Top View See Ordering Information www national com 6 PrintDate 1998 11 17 PrintTime 11 38 08 46711 ds005688 Rev No 4 cmserv Proof 6 ...

Page 8: ...ection for the external precision voltage source which drives the R 2R ladder VREF can range from 10 to 10 volts This is also the analog voltage input for a 4 quadrant multiplying DAC appli cation VCC Digital Supply Voltage This is the power supply pin for the part VCC can be from 5 to 15 VDC Operation is op timum for 15V The input threshold voltages are nearly in dependent of VCC See Typical Perf...

Page 9: ...t time critical When all DACs are updated a common strobe signal can then be used to cause all DACs to switch to their new analog output levels 3 0 TTL COMPATIBLE LOGIC INPUTS To guarantee TTL voltage compatibility of the logic inputs a novel bipolar NPN regulator circuit is used This makes the input logic thresholds equal to the forward drop of two diodes and also matches the temperature variatio...

Page 10: ...he available lad der current to the IOUT1 output pin These MOS switches op erate in the current mode with a small voltage drop across them and can therefore switch currents of either polarity This is the basis for the 4 quadrant multiplying feature of this DAC 5 1 1 Providing a Unipolar Output Voltage with the DAC in the Current Switching Mode A voltage output is provided by making use of an exter...

Page 11: ...ent of the 2 s complement processor data 512 D 511 or 1000000000 D 0111111111 If the ap plied digital input is interpreted as the decimal equivalent of a true binary word VOUT can be found by With this configuration only the offset voltage of amplifier 1 need be nulled to preserve linearity of the DAC The offset voltage error of the second op amp has no effect on linearity It presents a constant o...

Page 12: ...appears unusual since a ref erence voltage V is applied to the IOUT1 pin and the volt age output is the VREF pin This basic idea is shown in Figure 8 This VOUT range can be scaled by use of a non inverting gain stage as shown in Figure 9 Notice that this is unipolar operation since all voltages are positive A bipolar output voltage can be obtained by using a single op amp as shown in Figure 10 For...

Page 13: ...NPUT CODE DS005688 45 FIGURE 8 Voltage Mode Switching DS005688 46 FIGURE 9 Amplifying the Voltage Mode Output Single Supply Operation DS005688 47 FIGURE 10 Providing a Bipolar Output Voltage with a Single Op Amp www national com 12 PrintDate 1998 11 17 PrintTime 11 38 09 46711 ds005688 Rev No 4 cmserv Proof 12 ...

Page 14: ... kΩ resistor can be tem porarily connected from the inverting input to ground to pro vide a dc gain of approximately 15 to the VOS of the op amp and make the zeroing easier to sense 5 4 Full Scale Adjust The full scale adjust procedure depends on the application circuit and whether the DAC is operated in the current switching mode or in the voltage switching mode Tech niques are given below for al...

Page 15: ...P with an 8 bit data bus you will be directed to Section 6 1 0 The first consideration is will the DAC be interfaced to a µP with an 8 bit or a 16 bit data bus or used in the stand alone mode For the 8 bit data bus a second selection is made DS005688 49 FIGURE 12 Full Scale Adjust Current Switching with Bipolar Output Voltage DS005688 50 FIGURE 13 Full Scale Adjust Voltage Switching with a Unipola...

Page 16: ...gure No Data Bus 8 Bit Data Bus 6 1 0 Left Justified 6 1 1 6 2 1 16 6 2 2 16 6 2 3 16 16 Bit Data Bus 6 3 0 Single Buffered Double Buffered Flow Through 6 3 1 17 6 3 2 17 Not Applicable Stand Alone 6 4 0 Single Buffered Double Buffered Flow Through 6 4 1 17 6 4 2 17 NA These data possibilities are shown in Figure 15 Note that the justification of data depends on how the 10 bit data word is located...

Page 17: ...Left Justified Data DS005688 16 FIGURE 15 Fitting a 10 Bit Data Word into 16 Available Bit Locations DS005688 17 FIGURE 16 Input Connections and Controls for DAC1006 1007 1008 Left Justified Data www national com 16 PrintDate 1998 11 17 PrintTime 11 38 10 46711 ds005688 Rev No 4 cmserv Proof 16 ...

Page 18: ...third write strobe This is shown in the following diagram 6 2 3 Transfer Using an External Strobe This is similar to the previous operation except the XFER signal is not provided by the µP The timing diagram for this is 6 3 Interfacing to a 16 Bit Data Bus The interface to a 16 bit data bus is easily handled by con necting to 10 of the available bus lines This allows a wiring selected right justif...

Page 19: ...he circuit will perform an automatic transfer of the 10 bits of output data from the CPU to the DAC register as outlined in Section 6 2 1 Controlling Data Transfer for an 8 Bit Data Bus Since a double byte write is necessary to control the DAC with the INS8080A a possible instruction to achieve this is a PUSH of a register pair onto a stack in memory The 16 bit register pair word will contain the ...

Page 20: ...bytes is greatly simplified The HIGH byte is loaded into Output Register A ORA of the PIA and the LOW byte is loaded into ORB The 10 bit data transfer to the DAC and the corresponding analog output change occur simultaneously upon CB2 going LOW under program con trol The 10 bit data word in the DAC register will be latched and hence VOUT will be fixed when CB2 is brought back HIGH If both output p...

Page 21: ...mp This also has the advantage of eliminating noise spikes when changing digital codes DS005688 25 FIGURE 19 DAC1000 to MC6820 1 PIA Interface DS005688 55 NOTE DATA HOLD TIME REDUCED TO THAT OF DM74LS374 10 ns FIGURE 20 Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling www national com 20 PrintDate 1998 11 17 PrintTime 11 38 10 46711 ds005688 Rev No 4 cmserv Proof 20 ...

Page 22: ...e second op amp con verts IOUT2 to a voltage VOUT which is given by Note that N 0 or a digital code of all zeros is not allowed or this will cause the output amplifier to saturate at either VMAX depending on the sign of VIN To provide a digitally controlled divider the output op amp can be eliminated Ground the IOUT2 pin of the DAC and VOUT is now taken from the lower op amp which also drives the ...

Page 23: ...THIS PAGE IS IGNORED IN THE DATABOOK PrintDate 1998 11 17 PrintTime 11 38 11 46711 ds005688 Rev No 4 cmserv Proof 22 22 ...

Page 24: ...it DAC1006LCN DAC1006LCWM 0 10 9 bit DAC1007LCN 0 20 8 bit DAC1008LCN Package Outline N20A M20B Physical Dimensions inches millimeters unless otherwise noted Order Number DAC1006LCWM NS Package Number M20B www national com 23 23 PrintDate 1998 11 17 PrintTime 11 38 11 46711 ds005688 Rev No 4 cmserv Proof 23 ...

Page 25: ...r system or to affect its safety or effectiveness National Semiconductor Corporation Americas Tel 1 800 272 9959 Fax 1 800 737 7018 Email support nsc com www national com National Semiconductor Europe Fax 49 0 1 80 530 85 86 Email europe support nsc com Deutsch Tel 49 0 1 80 530 85 85 English Tel 49 0 1 80 532 78 32 Français Tel 49 0 1 80 532 93 58 Italiano Tel 49 0 1 80 534 16 80 National Semicon...

Page 26: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

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