DAC1006/1007/1008 — Simple Hookup for a “Quick Look”
(Continued)
Three operating modes are possible: flow through, single
buffered, or double buffered. The timing diagrams for these
are shown below:
6.3.1 Single Buffered
6.3.2 Double Buffered
6.4 Stand Alone Operation
For applications for a DAC which are not under µP control
(stand alone) there are two basic operating modes, single
buffered and double buffered. The timing diagrams for these
are shown below:
6.4.1 Single Buffered
6.4.2 Double Buffered
7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1006 family have been ori-
ented towards an ease of interface with all popular µPs. The
following sections discuss in detail a few useful interface
schemes.
7.1 DAC1001/1/2 to INS8080A Interface
Figure 18 illustrates the simplicity of interfacing the
DAC1006 to an INS8080A based microprocessor system.
The circuit will perform an automatic transfer of the 10 bits of
output data from the CPU to the DAC register as outlined in
Section 6.2.1, “Controlling Data Transfer for an 8-Bit Data
Bus.”
Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a “stack” in memory. The 16-bit
register pair word will contain the 10 bits of the eventual DAC
input data in the proper sequence to conform to both the re-
quirements of the DAC (with regard to left justified data) and
DS005688-21
FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus
DAC1006/1007/1008 (20-Pin Parts)
DS005688-51
DAC1006/1007/1008 (20-Pin Parts)
DS005688-52
DAC1006/1007/1008 (20-Pin Parts)
DS005688-53
DAC1006/1007/1008 (20-Pin Parts) (Note 12)
DS005688-54
Note 12: For a connection diagram of this operating mode use
Figure 16 for
the Logic and
Figure 17 for the Data Input connections.
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PrintDate=1998/11/17 PrintTime=11:38:10 46711 ds005688 Rev. No. 4
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